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參數(shù)資料
| 型號(hào)： | HYB3117800BSJ-50 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2M x 8-Bit Dynamic RAM |
| 中文描述： | 2M X 8 FAST PAGE DRAM, 50 ns, PDSO28 |
| 封裝： | 0.400 INCH, PLASTIC, SOJ-28 |
| 文件頁(yè)數(shù)： | 25/26頁(yè) |
| 文件大小： | 260K |
| 代理商： | HYB3117800BSJ-50 |
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Semiconductor Group
25
HYB 3117800BSJ-50/-60/-70
2M x 8-DRAM
Test Mode
As the HYB 3117800BSJ is organized internally as 1M x 16-bits, a test mode cycle using 2:1
compression can be used to improve test time. Note that in the 2M x 8 version the test time is
reduced by 1/2 for a N test pattern.
In a test mode “write” the data from each I/O pin is written into two 1M blocks simultaneously (all “1”
s or all “0” s). In test mode “read” each I/O output is used for indicating the test mode result. If the
internal two bits are equal, the I/O would indicate a “1”. If they were not equal, the I/O would indicate
a “0”. The WCBR cycle (WE, CAS before RAS) puts the device into test mode. To exit from test
mode, a “CAS before RAS refresh”, “RAS only refresh” or “Hidden refresh” can be used. Refresh
during test mode operation can be performed by normal read cycles or by WCBR refresh cylces.
Row addresses A0 through A9 have to kept high to perform a testmode entry cycle. All other
addresses are don’t care.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB3117800BSJ-70 | 2M x 8-Bit Dynamic RAM |
| HYB3117800BSJ-60 | 2M x 8-Bit Dynamic RAM |
| HYB3117800BSJL-50 | x8 Fast Page Mode DRAM |
| HYB3117800BSJL-60 | x8 Fast Page Mode DRAM |
| HYB3117800BSJL-70 | x8 Fast Page Mode DRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB3117800BSJ-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8 - Bit Dynamic RAM 2k Refresh |
| HYB3117800BSJ-70 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 8-Bit Dynamic RAM |
| HYB3117800BSJL-50 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| HYB3117800BSJL-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
| HYB3117800BSJL-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Fast Page Mode DRAM |
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