參數(shù)資料
型號: HYB25D256160CT-5
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbit Double Data Rate SDRAM
中文描述: 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 53/94頁
文件大?。?/td> 2808K
代理商: HYB25D256160CT-5
Data Sheet
53
Rev. 1.6, 2004-12
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Figure 28
Write to Precharge: Minimum DQSS, Odd Number of Data (1-bit Write), Interrupting (BL 4 or 8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 1 data element is written.
t
WR
is referenced from the first positive CK edge after the last desired data in pair.
The Precharge command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
1 = Can be don't care for programmed burst length of 4.
2 = For programmed burst length of 4, DQS becomes don't care at this point.
3 = This bit is correctly written into the memory array if DM is low.
4 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
PRE
Write
NOP
CK
CK
Command
Address
BA a, COL b
BA (a or all)
t
WR
t
RP
DI a-b
DQS
DQ
t
DQSS
(min)
2
1
1
DM
3
4
4
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