參數(shù)資料
型號(hào)： HYB25D256160BTL-5
廠(chǎng)商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbit Double Data Rate SDRAM
中文描述： 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁(yè)數(shù)： 24/94頁(yè)
文件大?。?/td> 3326K
代理商： HYB25D256160BTL-5
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
Data Sheet
30
Rev. 1.6, 2004-12
3.5
Operations
3.5.1
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must
be “opened” (activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see
Figure 7), which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the
t
RCD specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been “closed” (precharged). The minimum time interval between successive Active commands to the same
bank is defined by
t
RC. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by
t
RRD.
Figure 7
Activating a Specific Row in a Specific Bank
Figure 8
t
RCD and tRRD Definition
RA
BA
HIGH
RA = row address.
BA = bank address.
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
Don’t Care
ROW
ACT
NOP
COL
ROW
BA y
BA x
ACT
NOP
CK
Command
A0-A12
BA0, BA1
Don’t Care
RD/WR
tRCD
tRRD
RD/WR
NOP
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