參數(shù)資料
型號: HYB25D256160BT-6
廠商: INFINEON TECHNOLOGIES AG
英文描述: 256 Mbit Double Data Rate SDRAM
中文描述: 256兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 6/94頁
文件大?。?/td> 3326K
代理商: HYB25D256160BT-6
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Pin Configuration
Data Sheet
14
Rev. 1.6, 2004-12
Data Signals
×8 organization
A8, 2
DQ0
I/O
SSTL
Data Signal 7:0
B7, 5
DQ1
I/O
SSTL
C7, 8
DQ2
I/O
SSTL
D7, 11
DQ3
I/O
SSTL
D3, 56
DQ4
I/O
SSTL
C3, 59
DQ5
I/O
SSTL
B3, 62
DQ6
I/O
SSTL
A2, 65
DQ7
I/O
SSTL
Data Strobe
×8 organisation
E3, 51
DQS
I/O
SSTL
Data Strobe
Note: Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask
×8 organization
F3, 47
DM
I
SSTL
Data Mask
Note: DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
Data Signals
×16 organization
A8, 2
DQ0
I/O
SSTL
Data Signal 15:0
B9, 4
DQ1
I/O
SSTL
B7, 5
DQ2
I/O
SSTL
C9, 7
DQ3
I/O
SSTL
C7, 8
DQ4
I/O
SSTL
D9, 10
DQ5
I/O
SSTL
D7, 11
DQ6
I/O
SSTL
E9, 13
DQ7
I/O
SSTL
E1, 54
DQ8
I/O
SSTL
D3, 56
DQ9
I/O
SSTL
D1, 57
DQ10
I/O
SSTL
C3, 59
DQ11
I/O
SSTL
C1, 60
DQ12
I/O
SSTL
B3, 62
DQ13
I/O
SSTL
B1, 63
DQ14
I/O
SSTL
A2, 65
DQ15
I/O
SSTL
Data Strobe
×16 organization
E3, 51
UDQS
I/O
SSTL
Data Strobe Upper Byte
E7, 16
LDQS
I/O
SSTL
Data Strobe Lower Byte
Data Mask
×16 organization
Table 4
Pin Configuration of DDR SDRAM
Ball#/Pin#
Name
Pin
Type
Buffer
Type
Function
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