參數(shù)資料
型號(hào)： HYB25D128323C
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 13/53頁(yè)
文件大?。?/td> 734K
代理商： HYB25D128323C
Data Sheet
13
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Pin Configuration
DM3.. DM0
Input
Input Data Mask
: The DM signals are input mask signal for WRITE data. They mask
off a complete byte on the data bus. DMx = 1 prevents the corresponding byte from
being written. DM3 corresponds to DQ31..DQ24, DM2 to DQ23..DQ16, DM1 to
DQ15..DQ8, DM0 to DQ7..DQ0. DM signals are sampled on both edges of DQS.
Although DM pins are input-only, the DM loading is designed to match that of DQ and
DQS pins.
Voltage Reference
:
V
REF
is the reference voltage input signal.
V
REF
Input
V
DD,
V
SS
Supply
Power Supply
: Power and Ground for the internal logic.
V
DD
= 2.5 V
±
5% for L4.5, –4.5, and -5
2.5 V
–
5% <
V
DD
< 2.9 V for –3.6 and L3.6
2.5 V <
V
DD
< 2.9 V for –3 and –3.3
IO Power Supply
: Isolated Power and Ground for the output buffers to provide
improved noise immunity.
V
DDQ
= 2.5V
±
5%
Please do not connect No Connect, Reserved for Future Use pins.
Must be connected to low
V
DDQ,
V
SSQ
Supply
NC, RFU
MCL
–
–
Table 2
Pin
Signal and Pin Description
(cont’d)
IO Type Detailed Function
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128323C-3 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-3.3 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-3.6 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-4.5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-5 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
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