參數(shù)資料
型號(hào)： HYB25D128323C-5
廠商： INFINEON TECHNOLOGIES AG
英文描述： 128 Mbit DDR SGRAM
中文描述： 128兆的DDR SGRAM
文件頁(yè)數(shù)： 19/53頁(yè)
文件大?。?/td> 1166K
代理商： HYB25D128323C-5
Data Sheet
19
V1.7, 2003-07
HYB25D128323C[-3/-3.3/-3.6/-4.5/-5.0/L3.6/L4.5]
128 Mbit DDR SGRAM [4M x 32]
Register Set
Figure 7
DQS and DM Timing at Write
Prior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal
(DQSx) transits from Hi-Z to a valid logic low. This is referred to as the data strobe “Write Preamble”. Once the
burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal
(DQSx) transits from a valid logic low to Hi-Z. This is referred to as the data strobe “Write Postamble”,
t
WPST
. For
DDR SGRAM, data is written with a delay which is defined by the parameter
t
DQSS
(DDR write latency). This is
different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued.
Figure 8
DQS Pre/Postamble at Write
Q+2
Q+4
Q+1
DQSx
VIH
VTT
VIL
DMx
VIH
VTT
VIL
t
DMDQSS
t
DMDQSS
t
DMDQSH
t
DMDQSH
t
QDQSH
t
QDQSH
DQx
Q
Q+3
VIH
VTT
VIL
t
QDQSS
t
QDQSS
Input Data masked
CLK,
CLK#
VIH
VIL
WR
DQSx
VIH
VTT
VIL
DQx
Q
Q+1
Q+2
Q+3
VIH
VTT
VIL
t
DQSS
t
WPREH
t
WPRES
t
WPST
"Preamble"
"Postamble"
相關(guān)PDF資料
PDF描述
HYB25D128323C-L4.5 128 Mbit DDR SGRAM
HYB25D128323CL4.5 128 Mbit DDR SGRAM
HYB25D128323C-L3.6 128 Mbit DDR SGRAM
HYB25D128323ACL-33 JT 55C 55#22D SKT PLUG
HYB25D128323C 128 Mbit DDR SGRAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYB25D128323CL3.6 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-L3.6 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL-3.6 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323CL4.5 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
HYB25D128323C-L4.5 制造商:INFINEON 制造商全稱(chēng):Infineon Technologies AG 功能描述:128 Mbit DDR SGRAM
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