參數(shù)資料
型號(hào)： HYB25D128160TCL-7F
廠商： INFINEON TECHNOLOGIES AG
英文描述： MEMORY SPECTRUM
中文描述： 記憶譜
文件頁(yè)數(shù)： 68/85頁(yè)
文件大?。?/td> 3085K
代理商： HYB25D128160TCL-7F
Data Sheet
68
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Electrical Characteristics
Active to Autoprecharge delay
t
RAP
t
RCD
or
t
RASmin
10
t
RCD
or
t
RASmin
12
t
RCD
or t
RASmin
ns
2)3)4)5)
Active bank A to Active bank B
command
Write recovery time
Auto precharge write recovery +
precharge time
Internal write to read command
delay
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t
RRD
—
—
15
—
ns
2)3)4)5)
t
WR
t
DAL
15
—
15
—
15
ns
t
CK
2)3)4)5)
(
t
WR
/
t
CK
) + (
t
RP
/
t
CK
)
2)3)4)5)11)
t
WTR
2
—
1
—
1
—
t
CK
2)3)4)5)
t
XSNR
75
—
75
—
75
—
ns
2)3)4)5)
t
XSRD
200
—
200
—
200
—
t
CK
2)3)4)5)
t
REFI
—
15.6
—
15.6
—
15.6
μ
s
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V
(DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
10) Fast slew rate
≥
1.0 V/ns , slow slew rate
≥
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
V
IH(ac)
and
V
IL(ac)
.
11) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
12) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Table 19
Parameter
AC Timing - Absolute Specifications for PC3200, PC2700 and PC2100
Symbol –5
DDR400B
Min.
–6
–7
Unit
Note/ Test
Condition
1)
DDR333
Min.
DDR266A
Min.
Max.
Max.
Max.
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