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參數(shù)資料
| 型號： | HYB25D128160TCL-37 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MEMORY SPECTRUM |
| 中文描述： | 記憶譜 |
| 文件頁數(shù)： | 29/85頁 |
| 文件大?。?/td> | 3085K |
| 代理商： | HYB25D128160TCL-37 |
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Data Sheet
29
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.5.2
Subsequent to programming the mode register with CAS latency, burst type, and burst length, Read bursts are
initiated with a Read command, as shown on
Figure 9
.
The starting column and bank addresses are provided with the Read command and Auto Precharge is either
enabled or disabled for that burst access. If Auto Precharge is enabled, the row that is accessed starts precharge
at the completion of the burst, provided
t
RAS
has been satisfied. For the generic Read commands used in the
following illustrations, Auto Precharge is disabled.
During Read bursts, the valid data-out element from the starting column address is available following the CAS
latency after the Read command. Each subsequent data-out element is valid nominally at the next positive or
negative clock edge (i.e. at the next crossing of CK and CK).
Figure 10
shows general timing for each supported
CAS latency setting. DQS is driven by the DDR SDRAM along with output data. The initial low state on DQS is
known as the read preamble; the low state coincident with the last data-out element is known as the read
postamble. Upon completion of a burst, assuming no other commands have been initiated, the DQs goes High-Z.
Data from any Read burst may be concatenated with or truncated with data from a subsequent Read command.
In either case, a continuous flow of data can be maintained. The first data element from the new burst follows either
the last element of a completed burst or the last desired data element of a longer burst which is being truncated.
The new Read command should be issued x cycles after the first Read command, where x equals the number of
desired data element pairs (pairs are required by the 2n prefetch architecture). This is shown on
Figure 11
. A
Read command can be initiated on any clock cycle following a previous Read command. Nonconsecutive Read
data is illustrated on
Figure 12
. Full-speed Random Read Accesses: CAS Latencies (Burst Length = 2, 4 or 8)
within a page (or pages) can be performed as shown on
Figure 13
.
Reads
Figure 9
Read Command
BA
HIGH
CA = column address
BA = bank address
EN AP = enable Auto Precharge
DIS AP = disable Auto Precharge
CKE
CS
RAS
CAS
WE
A10
BA0, BA1
Don’t Care
CA
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
EN AP
DIS AP
CK
CK
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| HYB25D128160TCL-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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| HYB25D128160TE-3 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:MEMORY SPECTRUM |
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