Data Sheet
27
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Table 6
Name (Function)
Deselect (NOP)
No Operation (NOP)
Active (Select Bank And Activate Row)
Write (Select Bank And Column, And Start Write Burst)
Burst Terminate
Precharge (Deactivate Row In Bank Or Banks)
Auto Refresh Or Self Refresh (Enter Self Refresh Mode)
Mode Register Set
Truth Table 1a: Commands
CS
H
L
L
L
L
L
L
L
L
RAS CAS WE Address
X
X
X
H
H
H
L
H
H
H
L
H
H
L
L
H
H
L
L
H
L
L
L
H
L
L
L
MNE
NOP
NOP
Notes
1)2)
X
X
Bank/Row ACT
Bank/Col
Bank/Col
X
Code
X
Op-Code
1)2)
1)3)
Read
Write
BST
PRE
AR/SR
MRS
1)4)
1)4)
1)5)
1)6)
1)7)8)
1)9)
1) CKE is HIGH for all commands shown except Self Refresh.
2) Deselect and NOP are functionally interchangeable.
3) BA0-BA1 provide bank address and A0-A11 provide row address.
4) BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4);
A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature.
5) Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read
bursts with Auto Precharge enabled or for write bursts.
6) A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care”.
7) This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW.
8) Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
9) BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1,
BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to
be written to the selected Mode Register).
Table 7
Name (Function)
Write Enable
Write Inhibit
Truth Table 1b: DM Operation
DM
L
H
DQs
Valid
X
Notes
1)
1) Used to mask write data; provided coincident with the corresponding data.
1)