參數(shù)資料
型號(hào): HY62SF16806A-SM85C
英文描述: x16 SRAM
中文描述: x16的SRAM
文件頁(yè)數(shù): 3/10頁(yè)
文件大?。?/td> 188K
代理商: HY62SF16806A-SM85C
HY62SF16403A Series
Rev.11 / Jun.01
2
DESCRIPTION
The HY62SF16403A is a high speed, super low
power and 4Mbit full CMOS SRAM organized as
256K words by 16bits. The HY62SF16403A uses
high performance full CMOS process technology
and is designed for high speed and low power
circuit technology. It is particularly well-suited for
the high density low power system application.
This device has a data retention mode that
guarantees data to remain valid at a minimum
power supply voltage of 1.2V.
FEATURES
Fully static operation and Tri-state output
TTL compatible inputs and outputs
Battery backup
-. 1.2V(min) data retention
Standard pin configuration
-. 48-ball uBGA
Standby
Current(uA)
Product No.
Voltage
(V)
Speed (ns)
Operation
Current/Icc(mA)
LL
SL
Temperature
(
°C)
HY62SF16403A
1.7~2.3
85/100/120
3
10
3
0~70
HY62SF16403A-I
1.7~2.3
85/100/120
3
10
3
-40~85(I)
Note 1. Blank : Commercial, I : Industrial
2. Current value is max.
PIN CONNECTION
BLOCK DIAGRAM
PIN DESCRIPTION
Pin Name
Pin Function
Pin Name
Pin Function
/CS
Chip Select
I/O1~I/O16
Data Inputs/Outputs
/WE
Write Enable
A0~A17
Address Inputs
/OE
Output Enable
Vcc
Power(1.7~2.3)
/LB
Lower Byte Control(I/O1~I/O8)
Vss
Ground
/UB
Upper Byte Control(I/O9~I/O16)
NC
No Connection
MEMORY ARRAY
256K x 16
ROW
DECODER
SENSE
AMP
WRITE
DRIVER
DATA
I/O
BUFFER
I/O1
I/O8
I/O9
I/O16
COLUMN
DECODER
BLOCK
DECODER
PRE
DECODER
ADD
INPUT
BUFFER
A0
A17
/CS
/OE
/LB
/UB
/WE
1
2
3
4
5
6
A
B
C
D
E
F
G
H
uBGA
/LB
IO9
IO10
/OE
A0
A1
A2
NC
/UB
A3
A4
/CS
IO1
IO11 A5
A6
IO2
IO3
Vss
IO12 A17
A7
IO4
Vcc
IO13 NC
A16
IO5
Vss
IO15 IO14 A14
A15
IO6
IO7
IO16 NC
A12
A13
/WE
IO8
NC
A8
A9
A10
A11
NC
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