參數(shù)資料
型號: HY62SF16804A-DM85I
廠商: HYNIX SEMICONDUCTOR INC
元件分類: SRAM
英文描述: 512K X 16 STANDARD SRAM, 85 ns, PBGA48
封裝: MICRO, BGA-48
文件頁數(shù): 7/10頁
文件大?。?/td> 138K
代理商: HY62SF16804A-DM85I
HY62SF16804A
Rev.11 /Jan. 2002
5
TIMING DIAGRAM
READ CYCLE 1(Note 1,4)
READ CYCLE 2(Note 1,2,4)
tRC
tAA
Data Valid
Previous Data
tOH
ADDR
Data
Out
READ CYCLE 3(Note 1,2,4)
/CS
/UB, /LB
tACS
Data Valid
tCLZ(3)
tCHZ(3)
Data
Out
Notes:
1. A read occurs during the overlap of a low /OE, a high /WE, a low /CS1 and low /UB and /or /LB
2. /OE = VIL
3. Transition is measured + 200mV from steady state voltage.
This parameter is sampled and not 100% tested.
4. /CS in high for the standby, low for active
/UB and /LB in high for the standby, low for active
ADDR
tRC
/CS
tAA
tACS
tOH
Data Valid
High-Z
Data
Out
/UB ,/ LB
/OE
tBA
tOE
tCLZ(3)
tBLZ(3)
tOLZ(3)
tCHZ(3)
tBHZ(3)
tOHZ(3)
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