參數(shù)資料
型號(hào)： HY5R288HC
英文描述： -|2.5V|8K|40|Direct RDRAM - 288M
中文描述： - |為2.5V | 8K的| 40 |直接RDRAM的- 288M
文件頁(yè)數(shù)： 38/64頁(yè)
文件大?。?/td> 4542K
代理商： HY5R288HC
38
Rev.0.9/Dec.2000
Direct RDRAM
256/288-Mbit (512Kx16/18x32s) Preliminary
Power State Management
Table 16 summarizes the power states available to a Direct
RDRAM. In general, the lowest power states have the
longest operational latencies. For example, the relative
power levels of PDN state and STBY state have a ratio of
about 1:110, and the relative access latencies to get read data
have a ratio of about 250:1.
PDN state is the lowest power state available. The informa-
tion in the RDRAM core is usually maintained with self-
refresh; an internal timer automatically refreshes all rows of
all banks. PDN has a relatively long exit latency because the
TCLK/RCLK block must resynchronize itself to the external
clock signal.
NAP state is another low-power state in which either self-
refresh or REFA-refresh are used to maintain the core. See
“Refresh” on page 42 for a description of the two refresh
mechanisms. NAP has a shorter exit latency than PDN
because the TCLK/RCLK block maintains its synchroniza-
tion state relative to the external clock signal at the time of
NAP entry. This imposes a limit (t
NLIMIT
) on how long an
RDRAM may remain in NAP state before briefly returning
to STBY or ATTN to update this synchronization state.
Figure 45: summarizes the transition conditions needed for
moving between the various power states. At initialization,
the SETR/CLRR Reset sequence will put the RDRAM into
PDN state. The PDN exit sequence involves an optional
PDEV specification and bits on the CMD and SIO
IN
pins.
Once the RDRAM is in STBY, it will move to the
ATTN/ATTNR/ATTNW states when it receives a non-
broadcast ROWA packet or non-broadcast ROWR packet
with the ATTN command. The RDRAM returns to STBY
from these three states when it receives a RLX command.
Alternatively, it may enter NAP or PDN state from ATTN or
STBY states with a NAPR or PDNR command in an ROWR
packet. The PDN or NAP exit sequence involves an optional
PDEV specification and bits on the CMD and SIO0 pins.
The RDRAM returns to the ATTN or STBY state it was
originally in when it first entered NAP or PDN.
An RDRAM may only remain in NAP state for a time
t
NLIMIT
. It must periodically return to ATTN or STBY.
The NAPRC command causes a napdown operation if the
RDRAM’s NCBIT is set. The NCBIT is not directly visible.
It is undefined on reset. It is set by a NAP or NAPRC
command to the RDRAM, and it is cleared by an ACT
command to the RDRAM. It permits a controller to manage
a set of RDRAMs in a mixture of power states.
STBY state is the normal idle state of the RDRAM. In this
state all banks and sense amps have usually been left
precharged and ROWA and ROWR packets on the ROW
pins are being monitored. When a non-broadcast ROWA
packet or non-broadcast ROWR packet (with the ATTN
command) packet addressed to the RDRAM is seen, the
RDRAM enters ATTN state (see the right side of Figure
46:). This requires a time t
SA
during which the RDRAM
activates the specified row of the specified bank. A time
TFRMt
CYCLE
after the ROW packet, the RDRAM will be
able to frame COL packets (TFRM is a control register field
- see Figure 40:). Once in ATTN state, the RDRAM will
automatically transition to the ATTNW and ATTNR states
as it receives WR and RD commands.
Once the RDRAM is in ATTN, ATTNW, or ATTNR states,
it will remain there until it is explicitly returned to the STBY
Table 16: Power State Summary
Power
State
Description
Blocks consuming power
Power
State
Description
Blocks consuming power
PDN
Powerdown state.
Self-refresh
NAP
Nap state. Similar to PDN
except lower wake-up
latency.
Self-refresh or
REFA-refresh
TCLK/RCLK-Nap
STBY
Standby state.
Ready for ROW
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
ATTN
Attention state.
Ready for ROW and COL
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
ATTNR
Attention read state.
Ready for ROW and COL
packets.
Sending Q (read data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ mux transmitter
Core power
ATTNW
Attention write state.
Ready for ROW and COL
packets.
Ready for D (write data)
packets.
REFA-refresh
TCLK/RCLK
ROW demux receiver
COL demux receiver
DQ demux receiver
Core power
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