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參數(shù)資料
| 型號： | HY5DU283222AF-33 |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 128M(4Mx32) GDDR SDRAM |
| 中文描述： | 4M X 32 DDR DRAM, 0.6 ns, PBGA144 |
| 封裝： | 12 X 12 MM, 0.80 MM PITCH, FBGA-144 |
| 文件頁數(shù)： | 3/32頁 |
| 文件大?。?/td> | 355K |
| 代理商： | HY5DU283222AF-33 |
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DESCRIPTION
The Hynix HY5DU283222 is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the
point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the
clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data,
Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are inter-
nally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible
with SSTL_2.
FEATURES
2.5V +/- 5% V
DD
and V
DDQ
power supply
supports 300 / 275 / 250 / 200 MHz
2.8V +/- 5% V
DD
and V
DDQ
power supply
supports 500/450/400/350MHz
All inputs and outputs are compatible with SSTL_2
interface
12mm x 12mm, 144ball FBGA with 0.8mm pin pitch
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous - data transaction aligned to
bidirectional data strobe (DQS0 ~ DQS3)
Data outputs on DQS edges when read (edged DQ)
Data inputs on DQS centers when write (centered
DQ)
Data(DQ) and Write masks(DM) latched on the both
rising and falling edges of the data strobe
All addresses and control inputs except Data, Data
strobes and Data masks latched on the rising edges
of the clock
Write mask byte controls by DM (DM0 ~ DM3)
Programmable /CAS Latency 5, 4 and 3 supported
Programmable Burst Length 2 / 4 / 8 with both
sequential and interleave mode
Internal 4 bank operations with single pulsed /RAS
tRAS Lock-Out function supported
Auto refresh and self refresh supported
4096 refresh cycles 32ms
Half strength and Matched Impedance driver option
controlled by EMRS
ORDERING INFORMATION
Part No.
Power
Supply
Clock
Frequency
Max Data Rate
interface
Package
HY5DU283222AF-2
V
DD
2.8V
V
DDQ
2.8V
500MHz
1000Mbps/pin
SSTL_2
12mm x 12mm
144Ball FBGA
HY5DU283222AF-22
450MHz
900Mbps/pin
HY5DU283222AF-25
400MHz
800Mbps/pin
HY5DU283222AF-28
350MHz
700Mbps/pin
HY5DU283222AF-33
V
DD
2.5V
V
DDQ
2.5V
300MHz
600Mbps/pin
HY5DU283222AF-36
275MHz
550Mbps/pin
HY5DU283222AF-4
250MHz
500Mbps/pin
HY5DU283222AF-5
200MHz
400Mbps/pin
HY5DU283222AF
Rev. 0.7 / Jun. 2004 3
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| HY5DU283222AF-36 | 128M(4Mx32) GDDR SDRAM |
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| HY5DU283222AF-5 | 128M(4Mx32) GDDR SDRAM |
| HY5DU283222F-26 | 128M(4Mx32) GDDR SDRAM |
| HY5DU283222F-28 | 128M(4Mx32) GDDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU283222AF-36 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DU283222AF-4 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DU283222AF-5 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DU283222AQ | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
| HY5DU283222AQ-33 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:128M(4Mx32) GDDR SDRAM |
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