參數(shù)資料
型號(hào): HY5DU281622DLT-X
廠商: Hynix Semiconductor Inc.
英文描述: 128Mb-S DDR SDRAM
中文描述: 128Mb的- ? DDR SDRAM內(nèi)存
文件頁(yè)數(shù): 29/33頁(yè)
文件大?。?/td> 413K
代理商: HY5DU281622DLT-X
Rev. 0.0 / Apr. 2003 29
HY5DU28422D(L)T
HY5DU28822D(L)T
HY5DU281622D(L)T
AC CHARACTERISTICS I
(AC operating conditions unless otherwise noted)
Parameter
Symbol
DDR400 (D4)
DDR400 (D43)
Unit
Note
Min
Max
Min
Max
Row Cycle Time
tRC
60
-
55
-
ns
Auto Refresh Row Cycle Time
tRFC
70
-
70
-
ns
Row Active Time
tRAS
40
70K
40
70K
ns
Active to Read with Auto Precharge Delay
tRAP
tRCD
-
tRCD
-
ns
16
Row Address to Column Address Delay
tRCD
18
-
15
-
ns
Row Active to Row Active Delay
tRRD
10
-
10
-
ns
Column Address to Column Address Delay
tCCD
1
-
1
-
CK
Row Precharge Time
tRP
18
-
15
-
ns
Write Recovery Time
tWR
15
-
15
-
ns
Internal Write to Read Command Delay
tWTR
2
-
2
-
CK
Auto Precharge Write Recovery + Precharge Time
tDAL
(tWR/tCK)
+
(tRP/tCK)
-
(tWR/tCK)
+
(tRP/tCK)
-
CK
15
System Clock Cycle Time
CL = 3
tCK
5
10
5
10
ns
Clock High Level Width
tCH
0.45
0.55
0.45
0.55
CK
Clock Low Level Width
tCL
0.45
0.55
0.45
0.55
CK
Data-Out edge to Clock edge Skew
tAC
-0.7
0.7
-0.7
0.7
ns
DQS-Out edge to Clock edge Skew
tDQSCK
-0.55
0.55
-0.55
0.55
ns
DQS-Out edge to Data-Out edge Skew
tDQSQ
-
0.4
-
0.4
ns
Data-Out hold time from DQS
tQH
t
HP
-t
QHS
-
t
HP
-t
QHS
-
ns
1,10
Clock Half Period
tHP
min
(tCL,tCH)
-
min
(tCL,tCH)
-
ns
1,9
Data Hold Skew Factor
tQHS
-
0.5
-
0.5
ns
10
Data-out high-impedance window from CK,/CK
tHZ
tAC(Max)
tAC(Max)
ns
17
Data-out low-impedance window from CK, /CK
tLZ
-0.7
0.7
-0.7
0.7
ns
Input Setup Time (fast slew rate)
tIS
0.6
-
0.6
-
ns
2,3,5,6
Input Hold Time (fast slew rate)
tIH
0.6
-
0.6
-
ns
Input Setup Time (slow slew rate)
t
IS
0.6
-
0.6
-
ns
2,4,5,6
Input Hold Time (slow slew rate)
t
IH
0.6
-
0.6
-
ns
相關(guān)PDF資料
PDF描述
HY5DU281622DT-X 128Mb-S DDR SDRAM
HY5DU28422DLT-X 128Mb-S DDR SDRAM
HY5DU28422DT-X 128Mb-S DDR SDRAM
HY5DU28822DLT-X 128Mb-S DDR SDRAM
HY5DU28822DT-X 128Mb-S DDR SDRAM
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