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參數(shù)資料
| 型號： | HY5DU12822CLTP |
| 廠商： | Hynix Semiconductor Inc. |
| 英文描述： | CERAMIC CAPACITORS NP0 |
| 中文描述： | 產(chǎn)品512Mb DDR SDRAM |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 253K |
| 代理商： | HY5DU12822CLTP |
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Rev. 1.0 / Mar. 2005
16
1
HY5DU12422C(L)TP
HY5DU12822C(L)TP
HY5DU121622C(L)TP
DLL RESET
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon return-
ing to normal operation after having disabled the DLL for the purpose of debug or evaluation. The DLL is automatically
disabled when entering self refresh operation and is automatically re-enabled upon exit of self refresh operation. Any
time the DLL is enabled, 200 clock cycles must occur to allow time for the internal clock to lock to the externally
applied clock before an any command can be issued.
OUTPUT DRIVER IMPEDANCE CONTROL
The normal drive strength for all outputs is specified to be SSTL_2, Class II. Hynix also supports a half strength driver
option, intended for lighter load and/or point-to-point environments. Selection of the half strength driver option will
reduce the output drive strength by 50% of that of the full strength driver. I-V curves for both the full strength driver
and the half strength driver are included in this document.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY5DU12822CTP | 512Mb DDR SDRAM |
| HY5DU12822CTP-X | 512Mb DDR SDRAM |
| HY5DU281622DLT-X | 128Mb-S DDR SDRAM |
| HY5DU281622DT-X | 128Mb-S DDR SDRAM |
| HY5DU28422DLT-X | 128Mb-S DDR SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY5DU12822CLTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822CTP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822CTP-X | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822DF-D43 | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
| HY5DU12822DF-H | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:512Mb DDR SDRAM |
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