參數(shù)資料
型號： HY5DU121622CTP-5
廠商： HYNIX SEMICONDUCTOR INC
元件分類： DRAM
英文描述： 512Mb(32Mx16) GDDR SDRAM
中文描述： 32M X 16 DDR DRAM, 0.7 ns, PDSO66
封裝： 0.400 X 0.875 INCH, 0.65 MM PITCH, TSOP2-66
文件頁數(shù)： 26/29頁
文件大?。?/td> 233K
代理商： HY5DU121622CTP-5
Rev. 0.3 / Apr. 2005
26
1
HY5DU121622CTP
-Continue-
Note :
1.
This calculation accounts for tDQSQ(max), the pulse width distortion of on-chip circuit and jitter.
2.
Data sampled at the rising edges of the clock : A0~A12, BA0~BA1, CKE, /CS, /RAS, /CAS, /WE.
3.
For command/address input slew rate >=1.0V/ns
4.
For command/address input slew rate >=0.5V/ns and <1.0V/ns
This derating table is used to increase tIS/tIH in case where the input slew-rate is below 0.5V/ns.
Input Setup / Hold Slew-rate Derating Table.
5.
CK, /CK slew rates are >=1.0V/ns
6.
These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guaranteed by
design or tester correlation.
7.
Data latched at both rising and falling edges of Data Strobes(LDQS/UDQS) : DQ, LDM/UDM.
8.
Minimum of 200 cycles of stable input clocks after Self Refresh Exit command, where CKE is held high, is required to complete
Self Refresh Exit and lock the internal DLL circuit of DDR SDRAM.
9.
Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
value can be greater than the minimum specification limits for tCL and tCH).
10. tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS consists of
Parameter
Syl
4
5
6
t
Note
Min
Max
Min
Max
Min
Max
Data-In Setup Time to DQS-In (DQ & DM)
t
DS
0.4
-
0.4
-
0.45
-
ns
6,7,
11,
12,
13
Data-in Hold Time to DQS-In (DQ & DM)
t
DH
0.4
-
0.4
-
0.45
-
ns
Read DQS Preamble Time
t
RPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
Read DQS Postamble Time
t
RPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Write DQS Preamble Setup Time
t
WPRES
0
-
0
-
0
-
tCK
Write DQS Preamble Hold Time
t
WPREH
0.25
-
0.25
-
0.25
-
tCK
Write DQS Postamble Time
t
WPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
Mode Register Set Delay
t
MRD
2
-
2
-
2
-
tCK
Exit Self Refresh to Any Execute
Command
t
XSC
200
-
200
-
200
-
tCK
8
Average Periodic Refresh Interval
t
REFI
-
7.8
-
7.8
-
7.8
us
Input Setup / Hold Slew-rate
Delta tIS
Delta tIH
V/ns
ps
ps
0.5
0
0
0.4
+50
0
0.3
+100
0
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