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參數(shù)資料
| 型號： | HY57V561620T-H |
| 廠商： | HYNIX SEMICONDUCTOR INC |
| 元件分類： | DRAM |
| 英文描述： | 4Banks x 4M x 16Bit Synchronous DRAM |
| 中文描述： | 16M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 X 0.875 INCH, 0.80 MM PITCH, TSOP2-54 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 151K |
| 代理商： | HY57V561620T-H |
HY57V561620(L)T
4Banks x 4M x 16Bit Synchronous DRAM
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Revision 1.8 / Apr.01
DESCRIPTION
The HY57V561620T is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the main memory applications
which require large memory density and high bandwidth. HY57V561620 is organized as 4 banks of 4,194,304x16.
The HY57V561620T is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and
outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very
high bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline ( CAS latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count
sequence(sequential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate
command or can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined
design is not restricted by a `2N` rule.)
FEATURES
Single 3.3V
±
0.3V power supply
All device pins are compatible with LVTTL interface
JEDEC standard 400mil 54pin TSOP-II with 0.8mm
of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by UDQM and LDQM
Internal four banks operation
Auto refresh and self refresh
8192 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 and Full Page for Sequential Burst
- 1, 2, 4 and 8 for Interleave Burst
Programmable CAS Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock Frequency
Power
Organization
Interface
Package
HY57V561620T-HP
133MHz
4Banks x 4Mbits
x16
LVTTL
400mil 54pin TSOP II
HY57V561620T-H
133MHz
HY57V561620T-8
125MHz
HY57V561620T-P
100MHz
HY57V561620T-S
100MHz
HY57V561620LT-HP
133MHz
Lower
Power
HY57V561620LT-H
133MHz
HY57V561620LT-8
125MHz
HY57V561620LT-P
100MHz
HY57V561620LT-S
100MHz
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HY57V561620T-P | 4Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620T-S | 4Banks x 4M x 16Bit Synchronous DRAM |
| HY57V56820B | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V56820BL | 4 Banks x 8M x 8Bit Synchronous DRAM |
| HY57V641620HGLT-8I | CAP SMD 0805 .01UF 50V 5% |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HY57V561620T-HI | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x16 SDRAM |
| HY57V561620T-HP | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620T-I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16Mx16|3.3V|8K|75|SDR SDRAM - 256M |
| HY57V561620T-P | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 16Bit Synchronous DRAM |
| HY57V561620T-S | 制造商:HYNIX 制造商全稱:Hynix Semiconductor 功能描述:4Banks x 4M x 16Bit Synchronous DRAM |
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