參數(shù)資料
型號： HV66
廠商： Supertex, Inc.
英文描述： 32-Channel LCD Driver with Separate Backplane Output
中文描述： 32通道獨立的液晶背板輸出驅(qū)動器
文件頁數(shù)： 2/6頁
文件大?。?/td> 457K
代理商： HV66
2
Symbol
Parameter
Min
Max
Units
V
DD
V
PP
V
IH
V
IL
f
CLK
T
A
I
OD
Logic supply voltage
4.5
5.5
V
Output voltage*
0
32
V
High-level input voltage
2.4
V
DD
0.8
V
Low-level input voltage
0
V
Clock frequency
0
5
MHz
Operating free-air temperature
-40
+85
°
C
Allowable current through output diodes
200
mA
Notes:
*Output will not switch below 12V.
Power-up sequence should be the following:
1. Connect ground.
2. Apply V
DD
.
Power-down sequence should be the reverse of the above.
The V
PP
should not drop below V
DD
during operation.
3.
4.
Set all inputs (Data, CLK, Enable, etc.) to a known state.
Apply V
PP
.
Electrical Characteristics
(over recommended operating conditions unless noted)
DC Characteristics
(V
DD
= 5V, V
PP
= 32V, V
SS
= GND)
Symbol
Parameter
Min
Max
Units
Conditions
I
DD
V
DD
supply current
15
mA
V
DD
= V
DD
max
f
CLK
= 5MHz
Outputs high
I
PPQ
High voltage supply current
0.5
mA
0.5
mA
Outputs low
I
DDQ
V
OH
Quiescent V
DD
supply current
High-level output
0.5
mA
All V
IN
= V
SS
or V
DD
I
O
= 1mA, V
PP
= 24V
I
O
= -100
μ
A
I
O
= 1mA
I
O
= 100
μ
A
V
IH
= V
DD
V
IL
= 0V
I
O
= 10mA
I
O
= -10mA
Q
22
V
Data out
4.6
V
V
OL
Low-level output
Q
2
V
Data out
0.4
V
I
IH
I
IL
V
OLBP
V
OHBP
High-level logic input current
1
μ
A
Low-level logic input current
-1
μ
A
Low-level output voltage, backplane
3
V
High-level output voltage, backplane
29
V
AC Characteristics
(V
DD
= 5V, V
PP
= 32V, T
C
= 25
°
C), logic input rises/fall time = 10ns.
Symbol
Parameter
Min
Max
Units
Conditions
f
CLK
t
W
t
SU
t
H
t
ON
, t
OFF
t
ON
, t
OFF
t
DHL
t
DLH
t
DLE
t
WLE
t
SLE
t
BR
, t
BF
t
BR
- t
BF
Clock frequency
5
MHz
Clock width high or low
100
ns
Data set-up time before clock rises
25
ns
Data hold time after clock rises
50
ns
Time from latch enable or POL to HV
OUT
Time from POL to BP output
500
ns
C
L
= 20pF
C
L
= 20pF
C
L
= 10pF
C
L
= 10pF
500
ns
Delay time clock to data high to low
200
ns
Delay time clock to data low to high
200
ns
Delay time clock to LE low to high
50
ns
Width of LE pulse
100
ns
LE set-up time before clock rises
50
ns
BP
OUT
rise/fall time
BP
OUT
rise and fall difference
10
1000
μ
s
C
L
= 350nF
C
L
= 350nF
100
μ
s
Recommended Operating Conditions
HV66
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