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參數(shù)資料
| 型號： | HV623PG |
| 廠商： | SUPERTEX INC |
| 元件分類： | 顯示驅(qū)動器 |
| 英文描述： | 32-Channel 128-Level Amplitude Gray-Shade Display Column Driver |
| 中文描述： | EL DISPLAY DRIVER, PTFP64 |
| 封裝： | PLASTIC, QFP-64 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大?。?/td> | 64K |
| 代理商： | HV623PG |
12-124
HV623
Option 1
V
BIAS
(V)
0
0
Option 2
V
BIAS
(V)
-1.0
-2.0
V
CTL
(V)
0.1
1.0
R
CTL
(
)
56K
56K
I
PP
V
CTL
(V)
0
0
R
CTL
(
)
56K
56K
I
PP
(mA)
2
7
(mA)
4
5.5
Symbol
Parameter
Min
Typ
Max
Units
Conditions
f
SC
f
DIN
t
SS
t
HS
t
WA
t
DS
t
DH
t
WD
t
WLC
t
DLCR
t
DRCC1
t
DSL
t
CSC
t
WSC
t
CCC
t
WCC
Shift clock operating frequency
10.2
MHz
Data-in frequency
20.4
MHz
CSI/CSO pulse to shift clock setup time
40
ns
CSI/CSO pulse to shift clock hold time
0
ns
CSI pulse width
49
ns
Data to shift clock setup time
20
ns
Data to shift clock hold time
0
ns
Data-in pulse width
24
ns
Load count pulse width
98
ns
Load count to ramp delay
1
μ
s
μ
s
Ramp to count clock delay
0.47
Shift clock to load count delay time
98
ns
Shift clock cycle time
98
ns
Shift clock pulse width
49
ns
Count clock cycle time
98
ns
Count clock pulse width
49
ns
Note 1:
Count clock starts counting after 0.47
μ
s min. This is equivalent to a time duration for a linear ramp V
R
to ramp from 0 to 3V, assuming the minimum value of T
RR
,
ramp size time of 12
μ
s for V
R
= 80V.
AC Characteristics
(V
DD
= 5.5V, T
A
= 25
°
C)
Logic Timing
Electrical Characteristics
V
RAMP
Timing
Symbol
Note 2:
The maximum ramp hold time may be longer than 15
μ
s, but the output voltage HV
OUT
will droop due to leakage.
Table 1:
Schemes to control I
PP
bias current, typical I
PP
Parameter
Min
Typ
Max
Units
Conditions
t
CR
t
RR
t
HR2
t
FR
Cycle time of ramp signal
15
μ
s
μ
s
μ
s
μ
s
Ramp rise time
12
Ramp hold time
2
15
Ramp fall time
TBD
3
HV623
VCTL
VCTL
RCTL
RCTL
VBIAS
-
-
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