
Timing Diagrams
HT93LC66
5
December 7, 2000
Functional Description
TheHT93LC66isaccessedviaathree-wireserial
communication interface. The device is arranged
into 256 words by 16 bits or 512 words by 8 bits
depending whether the ORG pin is connected to
VCC or VSS. The HT93LC66 contains seven in-
structions: READ, ERASE, WRITE, EWEN,
EWDS, ERAL and WRAL. When the user
selectable internal organization is arranged
into 256 16 (512 8), these instructions are all
made up of 11(12) bits data: 1 start bit, 2 op code
bits and 8(9) address bits.
By using the control signal CS, SK and data in-
put signal DI, these instructions can be given to
the HT93LC66. These serial instruction data
presented at the DI input will be written into
the device at the rising edge of SK. During the
READ cycle, DO pin acts as the data output and
during the WRITE or ERASE cycle, DO pin in-
dicates the BUSY/READY status. When the
DO pin is active for read data or as a
BUSY/READY indicator the CS pin must be
high; otherwise DO pin will be in a
high-impedance state. For successful instruc-
tions, CS must be low once after the instruction
is sent. After power on, the device is by default
in the EWDS state. And, an EWEN instruction
must be performed before any ERASE or
WRITE instruction can be executed. The fol-
lowing are the functional descriptions and tim-
ing diagrams of all seven instructions.
READ
The READ instruction will stream out data at a
specified address on the DO pin. The data on
DO pin changes during the low-to-high edge of
SK signal. The 8 bits or 16 bits data stream is
preceded by a logical 0 dummy bit. Irrespec-
tive of the condition of the EWEN or EWDS in-
struction, the READ command is always valid
and independent of these two instructions. Af-
ter the data word has been read the internal ad-
dress will be automatically incremented by 1
allowing the next consecutive data word to be
read out without entering further address data.
TheaddresswillwraparoundwithCSHighun-
til CS returns to LOW.
EWEN/EWDS
The EWEN/EWDS instruction will enable or
disable the programming capabilities. At both
the power on and power off state the device auto-
matically entered the disable mode. Before a
WRITE, ERASE, WRAL or ERAL instruction is
given, the programming enable instruction
EWEN must be issued, otherwise the
ERASE/WRITE instruction is invalid. After the
EWEN instruction is issued, the programming
enable condition remains until power is turned
off or a EWDS instruction is given. No data can
be written into the device in the programming
disabled state. By so doing, the internal memory
data can be protected.
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