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參數(shù)資料
| 型號： | HT82V24 |
| 廠商： | Holtek Semiconductor Inc. |
| 英文描述： | 16-Bit, 15MSPS, 3-Channel CCD/CIS Analog Signal Processor |
| 中文描述： | 16位，15MSPS，3通道防治荒漠化公約/獨聯(lián)體模擬信號處理器 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 216K |
| 代理商： | HT82V24 |
HT82V24
Rev. 1.00
5
September 7, 2005
Functional Description
Integral Nonlinear (INL)
Integral nonlinear error refers to the deviation of each in-
dividual code from a line drawn from zero scale through
a positive full scale. The point used as zero scale occurs
1/2 LSB before the first code transition. A positive full
scale is defined as a level 1/2 LSB beyond the last code
transition. The deviation is measured from the middle of
each particular code to the true straight line.
Differential Nonlinear (DNL)
An ideal ADC exhibits code transitions that are exactly 1
LSB apart. DNL is the deviation from this ideal value.
Thus every code must have a finite width. No missing
codes guaranteed for the 16-bit resolution indicates that
all the 65536 codes respectively, are present in the
over-all operating range.
Offset Error
The first ADC code transition should occur at a level 1/2
LSB above the nominal zero scale voltage.
The offset error is the deviation of the actual first code
transition level from the ideal level.
Gain Error
The last code transition should occur for an analog
value of 1/2 LSB below the nominal full-scale voltage.
Gain error is the deviation of the actual difference be-
tween the first and the last code transitions and the ideal
difference between the first and the last code transi-
tions.
Sampling Delay
The sampling delay is the time delay that occurs when a
samplingedgeisappliedtotheHT82V24untiltheactual
sample of the input signal is held. Both CDSCLK1 and
CDSCLK2 sample the input signal during the transition
from high to low, so the sampling delay is measured
from each clock s falling edge to the instant the actual
internal sample is taken.
Internal Register Descriptions
Register
Name
Address
Data Bits
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
0
0
0
0
Don t care
3-CH CDS on
Clamp
Voltage
Enable
Power
Down
Input
Range
1 byte
out
MUX
0
0
1
0
RGB/
BGR
Red
Green
Blue
0
0
0
0
Red PGA
0
1
0
0
0
0
MSB
LSB
Green PGA
0
1
1
0
0
0
MSB
LSB
Blue PGA
1
0
0
0
0
0
MSB
LSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
1
0
MSB
LSB
Blue Offset
1
1
1
MSB
LSB
Internal Register Map (ADI Mode)
Register
Name
Address
Data Bits
A2
A1
A0
D8
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
0
0
0
1
Clamp Timing
Control
3-CH CDS on
Clamp
Voltage
Enable
Power
Down
Input
Range
Output
Format
MUX
0
0
1
DEL
RGB/
BGR
Red
Green
Blue
POSNNEG
VDEL
Red PGA
0
1
0
0
0
0
MSB
LSB
Green PGA
0
1
1
0
0
0
MSB
LSB
Blue PGA
1
0
0
0
0
0
MSB
LSB
Red Offset
1
0
1
MSB
LSB
Green Offset
1
1
0
MSB
LSB
Blue Offset
1
1
1
MSB
LSB
Internal Register Map (Wolfson Mode)
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