參數(shù)資料
型號(hào)： HT48RA1
廠商： Holtek Semiconductor Inc.
英文描述： Remote Type 8-Bit MCU
中文描述： 遠(yuǎn)程型8位微控制器
文件頁(yè)數(shù)： 14/39頁(yè)
文件大?。?/td> 308K
代理商： HT48RA1
HT48RA1/HT48CA1
Rev. 1.00
14
June 25, 2004
Timer/Event Counter
Two timer/event counters (TMR0, TMR1) are imple-
mented in the device. The Timer/Event Counter 0 con-
tains an 8-bit programmable count-up counter and the
clock may come from an external source or the system
clock. The Timer/Event Counter 1 contains an 16-bit
programmable count-up counter and the clock may
come from an external source or the system clock di-
vided by 4.
Of the two timer/event counters, using external clock in-
put allows the user to count external events, measure
time internals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
Only the Timer/Event Counter 0 can generate PFD sig-
nal by using external or internal clock, and PFD fre-
quency is determine by the equation f
INT
/[2 (256-N)].
There are 2 registers related to Timer/Event Counter 0;
TMR0(0DH), TMR0C(0EH). In Timer/Event Counter 0
counting mode (T0ON=1), writing TMR0 will only put the
written data to preload register (8 bits). The Timer/Event
Counter 0 preload register is changed by each writing
TMR0 operations. Reading TMR0 will also latch the
TMR0 to the destination. The TMR0C is the Timer/Event
Counter 0 control register, which defines the operating
mode, counting enable or disable and active edge.
The T0M0, T0M1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR0) pin. The timer mode functions as a normal timer
with the clock source coming from the f
INT
clock. The
pulse width measurement mode can be used to count
the high or low level duration of the external signal
(TMR0). The counting is based on the f
INT
clock.
In the event count or timer mode, once the Timer/Event
Counter 0 starts counting, it will count from the current
contents in the Timer/Event Counter 0 to FFH. Once
overflow occurs, the counter is reloaded from the
Timer/Event Counter 0 preload register and generates
the corresponding interrupt request flag (T0F; bit 5 of
INTC) at the same time.
In pulse width measurement mode with the T0ON and
T0E bits are equal to one, once the TMR0 has received
a transition from low to high (or high to low if the T0E bit
is 0) it will start counting until the TMR0 returns to the
original level and reset the T0ON. The measured result
will remain in the Timer/Event Counter 0 even if the acti-
vated transition occurs again. In other words, only one
cycle measurement can be done. Until setting the
T0ON, the cycle measurement will function again as
long as it receives further transition pulse. Note that, in
this operating mode, the Timer/Event Counter 0 starts
counting not according to the logic level but according to
the transition edges. In the case of counter overflows,
the counter 0 is reloaded from the Timer/Event Counter
0 preload register and issues the interrupt request just
like the other two modes.
To enable the counting operation, the timer ON
bit(T0ON; bit 4 of TMR0C) should be set to 1. In the
pulse width measurement mode, the T0ON will be
cleared automatically after the measurement cycle is
complete.ButintheothertwomodestheT0ONcanonly
be reset by instructions. The overflow of the
Timer/Event Counter 0 is one of the wake-up sources.
No matter what the operation mode is, writing a 0 to
ET0I can disabled the corresponding interrupt service.
In the case of Timer/Event Counter 0 OFF condition,
writing data to the Timer/Event Counter 0 preload regis-
ter will also load the data to Timer/Event Counter 0. But
if the Timer/Event Counter 0 is turned on, data written to
the Timer/Event Counter 0 will only be kept in the
Timer/Event Counter 0 preload register. The
Timer/Event Counter 0 will still operate until the overflow
occurs (a Timer/Event Counter 0 reloading will occur at
the same time).
When the Timer/Event Counter 0 (reading TMR0) is
read, the clock will be blocked to avoid errors. As this
may results in a counting error, this must be taken into
consideration by the programmer.
The bit 0~2 of the TMR0C can be used to define the
pre-scaling stages of the internal clock sources of
Timer/Event Counter 0. The definitions are as shown.
(Label
Function
T0PSC0
T0PSC1
T0PSC2
0
1
2
To define the prescaler stages,
T0PSC2, T0PSC1, T0PSC0=
000: f
INT
=f
SYS
/2
001: f
INT
=f
SYS
/4
010: f
INT
=f
SYS
/8
011: f
INT
=f
SYS
/16
100: f
INT
=f
SYS
/32
101: f
INT
=f
SYS
/64
110: f
INT
=f
SYS
/128
111: f
INT
=f
SYS
/256
T0E
3
To define the TMR0 active edge of
Timer/Event Counter 0
(0=active on low to high;
1=active on high to low)
T0ON
4
To enable/disable timer 0 counting
(0=disabled; 1=enabled)
5
Unused bit, read as 0
T0M0
T0M1
6
7
Todefinetheoperatingmode(T0M1,
T0M0)
01=Eventcountmode(externalclock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TMR0C Register
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