參數(shù)資料
型號(hào): HT48R10A-1
廠商: Holtek Semiconductor Inc.
英文描述: 8-Bit High Performance RISC-like Microcontroller Suitable for Multiple I/O Application(高性能、指令類似RISC的8位微控制器,用于多I/O接口設(shè)備)
中文描述: 8位高性能RISC架構(gòu)微控制器等的多個(gè)I / O應(yīng)用(高性能,指令類似的RISC的8位微控制器,用于多予適用/輸出接口設(shè)備)
文件頁數(shù): 14/45頁
文件大?。?/td> 321K
代理商: HT48R10A-1
HT48R10A-1
14
November 29, 2000
Reset
Therearethreewaysinwhicharesetcanoccur:
RES reset during normal operation
RES reset during HALT
WDT time-out reset during normal operation
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a "warm reset" that resets only the PC
and SP, leaving the other circuits in their origi-
nal state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the initial condition when the re-
set conditions are met. By examining the PD
and TO flags, the program can distinguish be-
tween different "chip resets".
TO PD
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal opera-
tion
1
1
WDT wake-up HALT
Note: "u" means "unchanged"
To guarantee that the system oscillator is
started and stabilized, the SST (System
Start-upTimer)providesanextra-delayof1024
system clock pulses when the system reset
(power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
When a system reset occurs, the SST delay is
added during the reset period. Any wake-up
from HALT will enable the SST delay.
The functional unit chip reset status are shown
below.
PC
000H
Interrupt
Disable
Prescaler
Clear
WDT
Clear. After master reset,
WDT begins counting
Timer/event
Counter
Off
Input/output
Ports
Input mode
SP
Points to the top of
the stack
/
1 , $ : * - /
4 1 0$ % $ /
Reset timing chart
Reset circuit
"
' # , $ % $ /
"
>
* ( 3
$ % $ /
2 % / $ , $ % $ /
: = 1 /1 0 0 ( $
* - . / $ #
Reset configuration
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