HT48E50
Rev. 0.00
9
September 29, 2004
Preliminary
supposed to be disabled prior to the table read in-
struction. It will not be enabled until the TBLH has
been backed up. All table related instructions require
two cycles to complete the operation. These areas
may function as normal program memory depending
upon the requirements.
Stack Register
STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 6 levels and is neither part of the
data nor part of the program space, and is neither read-
able nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledge signal, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the pro-
gram counter is restored to its previous value from the
stack.Afterachipreset,theSPwillpointtothetopofthe
stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a CALL is sub-
sequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 6 return ad-
dresses are stored).
Data Memory
RAM
The data memory has a capacity of 184 8 bits and is
divided into two functional groups: special function reg-
isters and general purpose data memory (160 8). Most
are read/write, but some are read only.
The special function registers include the indirect ad-
dressing registers (00H, 02H), the Bank Pointer
(BP;04H), Timer/Event Counter 0 (TMR0;0DH),
Timer/Event Counter 0 control register (TMR0C;0EH),
Timer/Event Counter 1 higher order byte register
(TMR1H;0FH), Timer/Event Counter 1 lower order byte
register (TMR1L;10H), Timer/Event Counter 1 control
register (TMR1C;11H), program counter lower-order
byte register (PCL;06H), memory pointer registers
(MP0;01H, MP1;03H), accumulator (ACC;05H), table
pointer (TBLP;07H), table higher-order byte register
(TBLH;08H), status register (STATUS;0AH), interrupt
control register (INTC;0BH), Watchdog Timer option
setting register (WDTS;09H), I/O registers (PA;12H,
PB;14H, PC;16H, PD;18H, PG;1EH) and I/O control
registers (PAC;13H, PBC;15H, PCC;17H, PDC;19H,
PGC;1FH). The remaining space before the 60H is re-
served for future expanded usage and reading these
locations will return the result 00H . The general pur-
pose data memory, addressed from 60H to FFH in Bank
0, is used for data and control information under instruc-
tion commands.
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations di-
rectly. Except for some dedicated bits, each bit in the
data memory can be set and reset by SET [m].i and
CLR [m].i . They are also indirectly accessible through
memory pointer registers (MP0 or MP1). The control
register of the EEPROM data memory is located at 40H
in Bank 1.
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write op-
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RAM Mapping