
Mnemonic
Description
F lag Affected
Instruction
Cycle
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with
result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with
result in ACC
Rotate data memory left through carry
None
None
C
C
None
None
C
C
1
1
(1)
1
1
(1)
1
1
(1)
1
1
(1)
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
None
None
None
1
1
(1)
1
Bit Operation
CLR [m].i
SE T [m].i
Clear bit of data memory
Set bit of data memory
None
None
1
(1)
1
(1)
Branch
J MP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RE T
RE T A,x
RE TI
J ump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement
to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result
in ACC
Skip if decrement data memory is zero with re-
sult in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data
to ACC
Return from interrupt
None
None
None
None
None
None
None
None
None
None
None
None
None
2
1
(2)
1
(2)
1
(2)
1
(2)
1
(3)
1
(3)
1
(2)
1
(2)
2
2
2
2
Table Read
TABRDC [m]
TABRDL [m]
Read ROM code (current page) to data memory
and TBLH
Read ROM code (last page) to data memory and
TBLH
None
None
2
(1)
2
(1)
HT48CXX/HT48RXX
30
25th May ’99