參數(shù)資料
型號(hào)： HT47C10L(44QFP)
英文描述： Microcontroller
中文描述： 微控制器
文件頁(yè)數(shù)： 14/38頁(yè)
文件大?。?/td> 287K
代理商： HT47C10L(44QFP)
HT47C10L
Rev. 1.10
14
October 2, 2002
Label (TMRC)
Bits
Function
0~2
Unused bit, read as 0
TE
3
To define the TMR active edge of timer/event counter
(0= active on low to high; 1= active on high to low)
TON
4
To enable/disable timer counting
(0= disabled; 1= enabled)
TN0
TN1
5
6
To define the operating mode (TN1, TN0)
10= Timer mode (Internal clock: f
SYS
)
01= Event counter mode (External clock: A/D clock from pad RCIN)
11= Pulse width measurement mode (RCIN, f
SYS
)
00= Unused
7
Unused bit, read as 0
TMRC register
the cycle measurement will function again as long as it
receives further transient pulse. Note that in this opera-
tion mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflow, the counter is re-
loaded from the timer/event counter preload register
and issues interrupt request just like the other two
modes.
To enable the counting operation, the timer on bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will automatically be
cleared after the measurement cycle is completed. But
in the other two modes, the TON can only be reset by in-
structions.
In the case of timer/event counter Off condition, writing
data to the timer/event counter preload register also re-
loads that data to the timer/event counter. But if the
timer/event counter turns On, data written to the
timer/event counter preload register is kept only in the
timer/event counter preload register. The timer/event
counter will still operate until overflow occurs.
When the timer/event counter (reading TMRAH) is read,
the clock will be blocked to avoid errors. As this may re-
sults in a counting error, this must be taken into consid-
eration.
It is strongly recommended to load first the desired
value into TMRBL, TMRBH, TMRAL, and TMRAH regis-
ters then turn on the related timer/event counter for
proper operation. Because the initial value of TMRBL,
TMRBH, TMRAL and TMRAH are unknown.
Example for Timer/event counter mode (disable interrupt):
clr tmrc
clr adcr.1
; set timer mode
clr intc.4
; clear timer/event counter interrupt request flag
mov a, low (65536-1000)
; give timer initial value
mov tmrbl, a
; count 1000 time and then overflow
mov a, high (65536-1000)
mov tmrbh, a
mov a, 01010000b
; timer clock source=f
SYS
and timer on
mov tmrc, a
p10:
clr wdt
snz intc.4
; polling timer/event counter interrupt request flag
jmp p10
clr intc.4
; clear timer/event counter interrupt request flag
; program continue
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