參數(shù)資料
型號: HT46R47(18SOP-A)
英文描述: Analog IC
中文描述: 模擬IC
文件頁數(shù): 40/45頁
文件大小: 297K
代理商: HT46R47(18SOP-A)
SET [m]
Set data memory.
Description
Each bit of the specified data memory is set to 1.
Operation
[m]
FFH
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SET [m].i
Set bit of data memory.
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i
1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SIZ [m]
Skip if increment data memory is 0.
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the following instruction, fetched during the current instruction execu-
tion, is discarded and a dummy cycle is replaced to get the proper instruction
(2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m]
([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
SIZA [m]
Increment data memory and place result in ACC, skip if 0.
Description
The contents of the specified data memory are incremented by 1. If the result
is 0, the next instruction is skipped and the result is stored in the accumula-
tor. The data memory remains unchanged. If the result is 0, the following in-
struction, fetched during the current instruction execution, is discarded and
a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise
proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC
([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
HT46R47
Rev. 1.40
40
July 18, 2001
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