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參數(shù)資料
| 型號： | HT36A0(48DIP) |
| 英文描述： | Microcontroller |
| 中文描述： | 微控制器 |
| 文件頁數(shù)： | 7/21頁 |
| 文件大小： | 229K |
| 代理商： | HT36A0(48DIP) |
HT36A0
Rev. 1.00
7
September 3, 2002
other type is for wavetable code, which is addressed by
the start address ST15~0. On the program type,
2
13
+ PC12~0. On the wave table
WA15~0= PF2~0
ROM type, WA15~0=ST15~0
2
5
.
Program memory
ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
8192 16 bits, addressed by the bank pointer, program
counter and table pointer.
Certain locations in the program memory of each bank
are reserved for special usage:
Location 000H on bank0
This area is reserved for the initialization program. Af-
ter chip reset, the program always begins execution at
location 000H on bank0.
Location 008H
This area is reserved for the Timer/Event Counter 0 in-
terrupt service program on each bank. If timer interrupt
resultsfromaTimer/EventCounter0overflow,andifthe
interrupt is enabled and the stack is not full, the program
begins execution at location 008H corresponding to its
bank.
Location 00CH
This area is reserved for the Timer/Event Counter 1
interrupt service program on each bank. If a timer in-
terrupt results from a Timer/Event Counter 1 overflow,
and if the interrupt is enabled and the stack is not full,
the program begins execution at location 00CH corre-
sponding to its bank.
Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m] (the cur-
rent page, 1 page=256 words) and TABRDL [m] (the
last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
higher-order byte of the table word are transferred to
the TBLH. The Table Higher-order byte register
(TBLH) is read only. The Table Pointer (TBLP) is a
read/write register (07H), which indicates the table lo-
cation. Before accessing the table, the location must
be placed in TBLP. The TBLH is read only and cannot
be restored. If the main routine and the ISR (Interrupt
Service Routine) both employ the table read instruc-
tion, the contents of the TBLH in the main routine are
likely to be changed by the table read instruction used
in the ISR. Errors can occur. In this case, using the ta-
ble read instruction in the main routine and the ISR si-
multaneouslyshouldbeavoided.However,ifthetable
readinstructionhastobeappliedinboththemainrou-
tine and the ISR, the interrupt should be disabled prior
to the table read instruction. It will not be enabled until
the TBLH has been backed up. All table related in-
structions need 2 cycles to complete the operation.
These areas may function as normal program mem-
ory depending upon user requirements.
Bank pointer
The program memory is organized into 8 banks and
each bank into 8192
to be bank pointer only when PFC is configured as
output mode. PFC is the control register of PF used to
control the input/output configuration. To function as
an output, the corresponding bit of the control register
16 bits program ROM. PF[2~0]
must be 0 . It will jump to the selection bank at the
next program counter whenever there is data moved
to the PF register. It should be note that the PF regis-
ter has to be cleared before setting to output mode.
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Program memory for each bank
Instruction(s)
Table Location
*12
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P12
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note:
*12~*0: Bits of table location
@7~@0: Bits of table pointer
P12~P8: Bits of current Program Counter
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