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參數(shù)資料
| 型號： | HSP48908VC-20 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Two Dimensional Convolver |
| 中文描述： | 8-BIT, DSP-CONVOLVER, PQFP100 |
| 封裝： | MQFP-100 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 110K |
| 代理商： | HSP48908VC-20 |
10
Initialization Register
The Initialization Register is used to appropriately configure
the convolver for a particular application. It is loaded through
the use of the ClN0-7 bus along with the CS an LD inputs.
Bit 0 defines the type of cascade mode to be used; Bits 1
and 2 select the number of delays to be included in the input
pixel data path; Bits 3 and 4 define the input and coefficient
data format; Bits 5 and 6 determine the type of rounding to
occur on the DOUT0-19 bus; Bits 7 an 8 define the shift
applied to the cascade input data. The complete definition of
the Initialization Register bits is give in Table 3.
Row Length Register
The Row Length Register is used to store the programmed
number of delays for the internal row buffers. The
Programmed delay is set equal to the row length (r) of the
input image. The input pixel data is stored in the row buffers
to allow corresponding pixels of adjacent rows to be
synchronously sent to the multiplier array for the convolution
operation. The Row Length Register is programmable with
the values from 0 to 1023, with 0 defined as a row length of
1024. Row lengths of 1 or 2 lead to meaningless results for a
3 x 3 kernel convolution, while a row length of 3 define 1 x 9
filter (See Operation Section). The Row Length Register is
written through the use of A0-2, CS and LD. Once the Row
Length Register has been loaded, the convolver must reset
before a new row length can be entered, or else new value
will be ignored. After RESET returns high, user has 1024
cycles of CLK to load the Row Length Register. After 1024
CLK cycles, the Row Length Register is automatically set to
0 (row length = 1024) and further writes to this register are
ignored.
Coefficient Registers (CREG0, CREG1)
The control logic contains two Coefficient Register banks CR
EG0 and CREG1. Each of these register banks is capable of
storing nine 8-bit filter coefficient values (3 x 3 Kernel). The
output of the registers are connected to the coefficient input
of the corresponding multiplier in the 3 x 3 multiplier array
(designated A through I). The register bank to be used for
the convolution is selectable by writing to the appropriate
address (See address decoder). All registers in a given bank
are enabled simultaneously, and one of the banks is always
active.
For most applications, only one of the register banks is
necessary. The user can simply load CREG0 after power up,
and use it for the entire convolution operation. (CREG0 is the
Default Register). The alternate register bank allows the
user to maintain two sets of filter coefficients and switch
between them in real time. The coefficient masks are loaded
via the CIN bus by using A0-2, CS and LD. The selection of
the particular register bank to be used in processing is also
done by writing to the appropriate address (see address
decoder). For example, if CREG0 is being used to provide
coefficients to the multipliers, CREG1 can be updated at a
low rate by an external processor; then at the proper time,
CREG1 can be selected, so that the new coefficient mask is
used to process the data. Thus, no clock cycles have been
lost when changing between alternate 3 x 3 filter kernels.
The nine coefficients must be loaded sequentially over the
ClN0-7 bus from A to I. The address of CREG0 or CREG1 is
placed on A0-2, and then the nine coefficients are written to
the corresponding Coefficient Register one at a time by
using the CS and LD inputs.
Address Decoder
The address decoder (see Figure 1) is used for writing to the
control logic of the HSP48908. Loading an Internal Register
is done by selecting the Destination Register with the A0-2
address lines, placing the data on CIN0-9, asserting the CS
and LD control lines. When either CS or LD goes high, the
data on the CIN0-9 lines is latched into the Addressed
Register. The address map for the A0-2 bus is shown in
Table 4.
While loading of the Control Logic Registers is
asynchronous to CLK, the Target Register in the control logic
TABLE 3. INITIALIZATION REGISTER DEFINITION
INITIALIZATION REGISTER
BIT 0
FUNCTION = CASCADE MODE
0
Multiplier input from internal row buffers.
1
Multiplier input from external buffers.
2 BIT 1
FUNCTION = INPUT DATA DELAY
0
0
No Data Delay Registers used.
0
1
One Data Delay Register used.
1
0
Two Data Delay Registers used.
1
1
Three data Delay Registers used.
BIT 3
FUNCTION = INPUT DATA FORMAT
0
Unsigned integer format.
1
Two’s complement format.
BIT 4
FUNCTION = COEFFICIENT DATA FORMAT
0
Unsigned integer format.
1
Two’s complement format.
6 BIT 5
FUNCTION = OUTPUT ROUNDING
0
0
No rounding.
0
1
Round to 16 bits (i.e., DOUT19-4).
1
0
Round to 8 bits (i.e., DOUT19-12).
1
1
Not Valid.
8 BIT 7
FUNCTION = CASI0-15 INPUT SHIFT
0
0
No shift.
0
1
Shift CASI0-15 left two.
1
0
Shift CASI0-15 left four.
1
1
Shift CASI0-15 left eight.
HSP48908
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| HSP48908VC-32 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Harris Corporation 功能描述: |
| HSP4890BVC-20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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| HSP50016 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Down Converter |
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