參數(shù)資料
型號(hào): HSP48908JC-20
廠商: HARRIS SEMICONDUCTOR
元件分類(lèi): 數(shù)字信號(hào)處理外設(shè)
英文描述: Two Dimensional Convolver
中文描述: 8-BIT, DSP-CONVOLVER, PQCC84
文件頁(yè)數(shù): 16/18頁(yè)
文件大?。?/td> 110K
代理商: HSP48908JC-20
16
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C
PARAMETER
SYMBOL
NOTES
-32 (32MHz)
-20 (20MHz)
UNITS
MIN
MAX
MIN
MAX
Clock Period
t
CYCLE
31
-
50
-
ns
Clock Pulse Width High
t
PWH
12
-
20
-
ns
Clock Pulse Width Low
t
PWL
13
-
20
-
ns
Data Input Setup Time
t
DS
13
-
14
-
ns
Data Input Hold Time
t
DH
0
-
0
-
ns
Clock to Data Out
t
OUT
-
16
-
22
ns
Address Setup Time
t
AS
13
-
13
-
ns
Address Hold Time
t
AH
0
-
0
-
ns
Configuration Data Setup Time
t
CDS
14
-
16
-
ns
Configuration Data Hold Time
t
CDH
0
-
0
-
ns
LD Pulse Width
t
LPW
12
-
20
-
ns
LD Setup Time
t
LCS
Note 4
25
-
30
-
ns
CIN0-7 Setup to CLK
t
CS
14
-
16
-
ns
CS Setup to LD
t
CSS
0
-
0
-
ns
CIN0-7 Hold Time from CLK
t
CH
0
-
0
-
ns
CS Hold from LD
t
CSH
0
-
0
-
ns
RESET Pulse Width
t
RPW
31
-
50
-
ns
FRAME Setup to Clock
t
FS
Note 5
21
-
25
-
ns
FRAME Pulse Width
t
FPW
31
-
50
-
ns
EALU Setup Time
t
ES
12
-
14
-
ns
EALU Hold Time
t
EH
0
-
0
-
ns
HOLD Setup Time
t
HS
11
-
12
-
ns
HOLD Hold Time
t
HH
1
-
1
-
ns
Output Enable Time
t
EN
Note 6
-
16
-
22
ns
Output Disable Time
t
OZ
Note 8
-
28
-
32
ns
Output Rise Time
t
R
From 0.8V to 2.0V, Note 8
-
6
-
6
ns
Output Fall Time
t
F
From 2.0V to 0.8V, Note 8
-
6
-
6
ns
NOTES:
4. This specification applies only to the case where the HSP48908 is being written to during an active convolution cycle. It must be met in order to
achieve predictable results at the next rising clock edge. In most applications, the configuration data and coefficients are loaded asynchronously
and the T
LCS
Specification may be disregarded.
5. While FRAME is an asynchronous signal, it must be deasserted a minimum of T
FS
ns prior to the rising clock edge which is to begin loading
pixel data for a new frame.
6. Transition is measured at
±
200mV from steady state voltage with loading as specified in test load circuit with C
L
= 40pF.
7. AC Testing is performed as follows: Input levels (CLK Input) 4.0 and 0V, Input levels (all other Inputs) 0V and 3.0V, Timing reference levels (CLK)
= 2.0V, (Others) = 1.5V; output load per test load circuit with C
L
= 40pF. Output transition is measured at V
OH
1.5V and V
OL
1.5V.
8. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
HSP48908
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