參數(shù)資料
型號(hào): HSP48901JC-20
廠商: HARRIS SEMICONDUCTOR
元件分類: 數(shù)字信號(hào)處理外設(shè)
英文描述: 3 x 3 Image Filter
中文描述: 8-BIT, DSP-DIGITAL FILTER, PQCC68
文件頁(yè)數(shù): 8/9頁(yè)
文件大?。?/td> 62K
代理商: HSP48901JC-20
8
Test Load Circuit
Address Hold Time
t
AH
t
CS
t
CH
t
LPH
t
LCS
t
HS
t
HH
t
FPW
t
FS
t
R
t
F
2
-
2
-
ns
Configuration Data Setup Time
10
-
12
-
ns
Configuration Data Hold Time
0
-
0
-
ns
LD Pulse Width
13
-
20
-
ns
LD Setup Time
Note 4
31
t
CYCLE
+2
-
40
t
CYCLE
+2
-
ns
HOLD Setup Time
10
12
ns
HOLD Hold Time
0
-
0
-
ns
FRAME Pulse Width
t
CYCLE
28
-
t
CYCLE
40
-
ns
FRAME Setup Time
Note 5
-
-
ns
Output Rise
From 0.8V to 2.0V
-
8
-
8
ns
Output Fall Time
From 2.0V to 0.8V
-
8
-
8
ns
NOTES:
4. This specification applies only to the case where a change in the active Coefficient Register is being selected during a convolution operation. It must
be met in order to achieve predictable results at the next rising clock edge. In most applications, this selection will be made asynchronously, and the
t
LCS
Specification may be disregarded.
5. While FRAME is asynchronous with respect to CLK, it must be deasserted a minimum of t
FS
ns prior to the rising clock edge which is to begin loading
new pixel data for the next frame.
6. AC Testing is performed as follows: Input levels (CLK Input) = 4.0V and 0V; input levels (all other inputs) = 0V to 3.0V; input timing reference levels:
(CLK) = 2.0V, (others) = 1.5V; other timing references: V
OH
1.5V, V
OL
1.5V; output load test load circuit with C
L
= 40pF.
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C
PARAMETER
SYMBOL
NOTES
TEST
CONDITIONS
-30
-40
UNITS
MIN
MAX
MIN
MAX
DUT
EQUIVALENT CIRCUIT
1.5V
I
OL
I
OH
(NOTE 7) C
L
S
1
±
NOTES:
7. Includes stray and jig capacitance.
8. Switch S
1
Open for I
CCSB
and I
CCOP
Tests.
HSP48901
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