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參數(shù)資料
| 型號： | HSP48410JC-40 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | CONN MEMORY CARD NORMAL I/O |
| 中文描述： | 24-BIT, DSP-HISTOGRAM PROCESSOR, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 84K |
| 代理商： | HSP48410JC-40 |
6
Functional Block Diagram
Histogram Mode
This is the fundamental operation for which this chip was
intended. When this mode is selected, the chip configures
itself as shown in the Block Diagram of Figure 2. The pixel
data is sampled on the rising edge of clock and used as the
read address to the RAM array. The data contained in that
address (or bin) is then incremented by 1 and written back
into the RAM at the same address.
At the same time, the new value is also displayed on the DIO
bus. This procedure continues until the circuit is interrupted
by START returning high. When START is high, the RAM
write is disabled, the read address is taken from the Pixel
Input bus, and the chip acts as if it is in LUT(read) mode.
Figure 3 shows histogram mode timing. START is used to
disregard the data on PIN0-9 at DATA2. START is sampled
on the rising edge of clock, but is delayed internally by 3
cycles to match the latency of the Address Generator. Data
is clocked onto the DIO bus on the rising edge of CLK. RD
acts as output enable.
DIO
I/F
MUX
MUX
R
DECODE
COUNTER
ADDRESS
GENERATOR
24X1024
RAM
ADDER
INPUT
CONTROL
∑
IN
OUT
ADDRESS
DIO 0-23
PIN 0-9
DIN 0-23
FCT 0-2
LD
CLK
START
MUX
CONTROL
SIGNALS
IOADD 0-9
RD
WR
UWS
FUNCTION
CONTROL
TO ADDRESS GENERATOR
TO OUTPUT STAGE
FC
TO RAM
ALL REGISTERS ARE CLOCKED BY CLK
R
R
R
R
FIGURE 1. FUNCTIONAL BLOCK DIAGRAM
R
ADDRESS
GENERATOR
RAM
S
IN
OUT
WR
ADDRESS
“1”
DIO
0-23
PIN 0-9
START
CONTROL
DIO
I/F
M
“0”
R
R
RD
FIGURE 2. HISTOGRAM MODE BLOCK DIAGRAM
CLK
PIN 0-9
START
DIO 0-23
(RD LOW)
DATA 0 DATA 1 DATA 2 DATA 3 DATA 4
OUT 0
OUT 1
OUT 2
DATA 5
ORIGINAL BIN CONTENTS
ARE NOT UPDATED
FIGURE 3. HISTOGRAM MODE TIMING
HSP48410
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