- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄371898 > HSP48410883 (Intersil Corporation) Histogrammer/Accumulating Buffer PDF資料下載
參數(shù)資料
| 型號(hào)： | HSP48410883 |
| 廠商： | Intersil Corporation |
| 英文描述： | Histogrammer/Accumulating Buffer |
| 中文描述： | Histogrammer /累積緩沖區(qū) |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大?。?/td> | 84K |
| 代理商： | HSP48410883 |
4
Pin Description
NAME
PLCC PIN
TYPE
DESCRIPTION
CLK
1
I
Clock Input. This input has no effect on the chips functionality when the chip is programmed
to an asynchronous mode. All signals denoted as synchronous have their timing specified
with reference to this signal.
PIN0-9
3-11, 83
I
Pixel Input. This input bus is sampled by the rising edge of clock. It provides the on-chip RAM
with address values in Histogram, Bin Accumulate and LUT(write) mode. During Asynchro-
nous modes it is unused.
LD
15
I
The Load pin is used to load the FCT0-2 bits into the FCT Registers. (See below).
FCT0-2
16-18
I
These three pins are decoded to determine the mode of operation for the chip. The signals
are sampled by the rising edge of LD and take effect after the rising edge of LD. Since the
loading of this function is asynchronous to CLK, it is necessary to disable the START pin dur-
ing loading and enable START at least 1 CLK cycle following the LD pulse.
START
14
I
This pin informs the on-chip circuitry which clock cycle will start and/or stop the current mode
of operation. Thus, the modes are asynchronously selected (via LD) but are synchronously
started and stopped. This input is sampled by the rising edge of CLK. The actual function of
this input depends on the mode that is selected. START must always be held high (disabled)
when changing modes. This will provide a smooth transition from one mode to the next by
allowing the part to reconfigure itself before a new mode begins. When START is high,
LUT(read) mode is enabled except for Delay and Delay and Subtract modes.
FC
12
I
Flash Clear. This input provides a fully asynchronous signal which effectively resets all bits
in the RAM Array and the input and output data paths to zero.
DIN0-23
58-63,
65-82
I
Data Input Bus. Provides data to the Histogrammer during Bin Accumulate, LUT, Delay and
Delay and Subtract modes. Synchronous to CLK.
DIO0-23
33-40,
42-57
I/O
Asynchronous Data Bus. Provides RAM access for a microprocessor in preconditioning the
memory array and reading the results of the previous operation. Configurable as either a 24
or 16-bit bus.
IOADD0-9
22-31
I
RAM address in asynchronous modes. Sampled on the falling edge of WR or RD.
UWS
21
I
Upper Word Select. In 16-bit Asynchronous mode, a one on this pin denotes the contents of
DIO0-7 as being the upper eight bits of the data in or out of the Histogrammer. A zero means
WR
19
I
Write enable to the RAM for the data on DIO0-23 when the HSP48410 is configured in one
of the asynchronous modes. Asynchronous to CLK.
RD
13
I
Read control for the data on DIO0-23 in asynchronous modes. Output enable for DIO0-23
in other modes. Asynchronous to CLK.
V
CC
2, 32
+5V. 0.1
μ
F capacitors between the V
CC
and GND pins are recommended.
GND
20, 41, 64, 84
Ground
NOTES:
1. An overbar denotes an active low signal.
2. Bit 0 is the LSB on all busses.
HSP48410
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HSP48410JC-33 | CONN MEMORY CARD REV BOTTOM PCB |
| HSP48410JC-40 | CONN MEMORY CARD NORMAL I/O |
| HSP48901GC-20 | 3 x 3 Image Filter |
| HSP48901GC-30 | 3 x 3 Image Filter |
| HSP48901JC-20 | 3 x 3 Image Filter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP48410GC-33 | 制造商:Rochester Electronics LLC 功能描述:HISTOGRAMER 84 PGA, 33MHZ, COMM - Bulk |
| HSP48410GC-40 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Histogrammer/Accumulating Buffer |
| HSP48410GM-25/883 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| HSP48410GM-33/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Histogrammer/Accumulating Buffer |
| HSP48410JC-33 | 制造商:Rochester Electronics LLC 功能描述:HISTOGRAMER 84 PLCC, 33MHZ, COMM - Bulk |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。