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參數(shù)資料
| 型號： | HSP45256JI-33 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Binary Correlator |
| 中文描述： | 8-BIT, DSP-CORRELATOR, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 11/23頁 |
| 文件大?。?/td> | 154K |
| 代理商： | HSP45256JI-33 |
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TABLE 7. MS OFFSET REGISTER B
DESTINATION ADDRESS = 5 (101)
BIT
POSITION
FUNCTION
DESCRIPTION
7-1
Reserved
Reserved. Program to zero.
0
Offset Register B MSB
OFFB8: Most significant bit of Offset Register B. In dual correlator mode, this register is used for the
correlator whose output appears on the AUXOUT pins.
TABLE 8. LS OFFSET REGISTER B
DESTINATION ADDRESS = 6 (110)
BIT
POSITION
FUNCTION
DESCRIPTION
7-0
Offset Register B LSB
OFFB0-7: Least significant bits of Offset Register B.
HSP45256
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