參數(shù)資料
型號(hào)： HSP45256GC-33
廠商： HARRIS SEMICONDUCTOR
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： Binary Correlator
中文描述： 8-BIT, DSP-CORRELATOR, CPGA85
文件頁(yè)數(shù)： 20/23頁(yè)
文件大?。?/td> 154K
代理商： HSP45256GC-33
20
Reloading Data During Operation
RLOAD and CLOAD are asynchronous signals that are
designed to be driven by the memory interface signals of a
microprocessor. TXFR is synchronized to CLK so that the
mask or reference data is updated on a specific clock cycle.
In the normal mode of operation, the user loads the
reference and mask memories, then pulses TXFR to use
that data. The correlator uses the new mask or reference
information immediately. Loading of the reference and mask
data remains asynchronous as long as there is at least one
cycle of CLK between the rising edge of RLOAD or CLOAD
and the TXFR pulse.
If the system timing makes it necessary for TXFR and
RLOAD and/or CLOAD to be active during the same clock
cycle, then they must be treated as synchronous signals; the
timing for this case is shown in Figure 24 and given in the AC
Timing Specifications (t
THCL
and t
CLLH
). In this example,
data is loaded during clock cycle 1 and transferred on the
rising edge of CLK that occurs in clock cycle two. Another
set of data is loaded during clock cycle 2, which will be
transferred by a later TXFR pulse. The sequence of events is
as follows:
1. In clock cycle 1, TXFR becomes active at least t
TH
nano-
seconds after the rising edge of CLK.
2. RLOAD and/or CLOAD pulses low; the timing is not
critical as long as its rising edge occurs before the end of
clock cycle 1. If this condition is not met, it is undeter-
mined whether the data loaded by this pulse will be trans-
ferred by the current TXFR pulse.
3. The rising edge of TXFR occurs while CLK is high during
clock cycle 2. The margin between the rising edge of
TXFR and the falling edge of CLK is defined by t
THCL
.
4. RLOAD and/or CLOAD pulses low. The rising edge of
RLOAD and CLOAD must occur after the falling edge of
CLK. The margin between the two is defined by t
CLLH
.
The time from the rising edge of TXFR to the falling edge of
CLK must be greater than t
THCL
, and the time from the
falling edge of CLK to the rising edge of RLOAD or CLOAD
must be greater than t
s
. If this timing is violated, the data
being transferred by the TXFR pulse shown may or may not
include the data loaded in clock cycle 2.
CLK
TXFR
RLOAD,
CLOAD
CLOCK CYCLE 1
CLOCK CYCLE 2
FIGURE 24. LOADING AND TRANSFERRING DATA DURING THE SAME CLOCK CYCLE
t
TH
1.
2.
t
THCL
3.
t
CLLH
4.
HSP45256
相關(guān)PDF資料
PDF描述
HSP45256JI-25 Binary Correlator
HSP45256JI-33 Binary Correlator
HSP45256 Binary Correlator
HSP45256883 Binary Correlator
HSP45256JC-25 Binary Correlator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HSP45256GM-20/883 制造商:Rochester Electronics LLC 功能描述:BINARY CORRELATOR 85 PGA, 20MHZ, MIL 883 - Bulk 制造商:Harris Corporation 功能描述:
HSP45256GM-25/883 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator
HSP45256JC-25 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator
HSP45256JC-33 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator
HSP45256JI-25 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Binary Correlator
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*