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參數資料
| 型號： | HSP45116-DB |
| 廠商： | Intersil Corporation |
| 英文描述： | HSP45116 Daughter Board |
| 中文描述： | HSP45116子板 |
| 文件頁數： | 16/18頁 |
| 文件大?。?/td> | 129K |
| 代理商： | HSP45116-DB |
16
AC Electrical Specifications
V
CC
= 5.0V
±
5%, T
A
= 0
o
C to 70
o
C (Note 5)
PARAMETER
SYMBOL
NOTES
-15 (15MHz)
-25 (25.6MHz)
-33 (33MHz)
UNITS
MIN
MAX
MIN
MAX
MIN
MAX
CLK Period
t
CP
66
-
39
-
30
-
ns
CLK High
t
CH
26
-
15
-
12
-
ns
CLK Low
t
CL
26
-
15
-
12
-
ns
WR Low
t
WL
26
-
15
-
12
-
ns
WR High
t
WH
26
-
15
-
12
-
ns
Setup Time; AD0-1, CS to WR Going High
t
AWS
18
-
13
-
13
-
ns
Hold Time; AD0, AD1, CS from WR Going High
t
AWH
0
-
0
-
0
-
ns
Setup Time C0-15 from WR Going High
t
CWS
20
-
15
-
15
-
ns
Hold Time C0-15 from WR Going High
t
CWH
0
-
0
-
0
-
ns
Setup time WR High to CLK High
t
WC
7
20
-
16
-
12
-
ns
Setup Time MOD0-1 to CLK Going High
t
MCS
20
-
15
-
15
-
ns
Hold Time MOD0-1 from CLK Going High
t
MCH
0
-
0
-
0
-
ns
Setup Time PACI to CLK Going High
t
PCS
25
-
15
-
11
-
ns
Hold Time PACI from CLK Going High
t
PCH
0
-
0
-
0
-
ns
Setup ENPHREG, ENCFREG, ENOFREG,
ENPHAC,ENTIREG,CLROFR,PMSEL,LOAD,ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
t
ECS
18
-
12
-
12
-
ns
Hold Time ENPHREG, ENCFREG, ENOFREG, EN-
PHAC, ENTIREG, CLROFR, PMSEL, LOAD, ENI,
ACC, BINFMT, PEAK, MODPI/2PI, SH0-1, RBYTILD
from CLK Going High
t
ECH
0
-
0
-
0
-
ns
Setup Time RIN0-18, IMIN0-18 to CLK
Going High
t
DS
18
-
12
-
12
-
ns
Hold Time RIN0-18, IMIN0-18 from CLK
Going High
t
DH
0
-
0
-
0
-
ns
CLK to Output Delay RO0-19, IO0-19
t
DO
-
40
-
24
-
19
ns
CLK to Output Delay DET0-1
t
DEO
-
40
-
27
-
20
ns
CLK to Output Delay PACO
t
PO
-
30
-
20
-
12
ns
CLK to Output Delay TICO
t
TO
-
30
-
20
-
12
ns
Output Enable Time OER, OEI, OEREXT, OEIEXT
t
OE
-
25
-
20
-
20
ns
OUTMUX0-1 to Output Delay
t
MD
-
40
-
28
-
26
ns
Output Disable Time
t
OD
6
-
20
-
15
-
15
ns
Output Rise, Fall Time
t
RF
6
-
8
-
8
-
6
ns
NOTES:
5. AC testing is performed as follows: Input levels (CLK Input) 4.0V and 0V; input levels (all other inputs) 0V and 3.0V; timing reference levels (CLK)
2.0V; all others 1.5V. Output load per test load circuit with switch closed and C
L
= 40pF. Output transition is measured at V
OH
≥
1.5V and V
OL
≤
1.5V.
6. Controlled via design or process parameters and not directly tested. Characterized upon initial design and after major process and/or design
changes.
7. Applicable only when outputs are being monitored and ENCFREG, ENPHREG, or ENTIREG is active.
HSP45116
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PDF描述 |
|---|---|
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相關代理商/技術參數 |
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|---|---|
| HSP45116DB-EVAL | 功能描述:子卡和OEM板 HSP45116 DAUGHTER EV EVAL BRD RoHS:否 制造商:BeagleBoard by CircuitCo 產品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| HSP45116GC-15 | 制造商:Rochester Electronics LLC 功能描述:16 BIT NUMERICALLY CONTROLLED OSC/MOD 144 PGA, 15MHZ, COMM - Bulk |
| HSP45116GC-25 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Numerically Controlled Oscillator/Modulator |
| HSP45116GC-33 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Numerically Controlled Oscillator/Modulator |
| HSP45116GC-45 | 制造商:Harris Corporation 功能描述: |
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