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參數(shù)資料
| 型號： | HSP43891VC-30 |
| 廠商： | HARRIS SEMICONDUCTOR |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Digital Filter |
| 中文描述： | 9-BIT, DSP-DIGITAL FILTER, PQFP100 |
| 文件頁數(shù)： | 10/18頁 |
| 文件大?。?/td> | 142K |
| 代理商： | HSP43891VC-30 |
10
Detailed operation of the DF to perform a basic 8-tap, 9-bit
coefficient, 9-bit data, 30MHz FIR filter is best understood by
observing the schematic (Figure 3) and timing diagram
(Figure 4). The internal pipeline length of the DF is four (4)
clock cycles, corresponding to the register levels CREG (or
XREG), MREG0, MREG1, and TREG (Figures 1 and 2).
Therefore, the delay from presentation of data and
coefficients at the DIN0-8 and CIN0-8 inputs to a sum
appearing at the SUM0-25 output is: k + Td, where k = filter
length and Td = 4, the internal pipeline delay of the DF. After
the pipeline has filled, a new output sample is available
every clock. The delay to last sample output from last
sample input is Td. The output sums, Y
N
, shown in the
timing diagram are derived from the sum-of-products
equation.
7
Σ
K
0
=
Y
N
=
C
K
X
N K
–
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
C
7
C
6
C
5
C
4
C
3
C
2
C
1
C
0
C
7
C
6
C
5
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
X
0
X
1
X
2
X
3
X
4
X
5
X
6
X
7
X
8
X
9
X
10
X
11
X
12
X
13
X
14
X
15
X
16
X
17
X
18
0
1
2
3
4
5
6
7
0
Y
7
Y
8
Y
9
Y
10
Y
11
Y
12
Y
13
Y
14
CLK
RESET
ERASE
DIN0-8
DIENB
CIN0-8
CIENB
ADR0-2
SUM0-25
SHADD
SENBL
SENBH
DCM0-1
0
FIGURE 4. HSP43891 30MHz, 8-TAP FIR FILTER TIMING
+5V
ADR1
ADR0
ADR2
V
CC
SHADD
SENBH
SENBL
DIN0-8
DIENB
CLK
CIN0-8
CIENB
DCM1
DCM0
RESET
ERASE
V
SS
COENB
COUT0-8
SUM0-25
26
SUM
OUT
(Y
N
)
9
NC
HSP43891
DF1
9
+5V
26
9
9
9
30MHz
CLOCK
Q
Q
C
D
SAMPLE
DATA IN (X
N
)
9x16 COEFF
RAM/ROM
A
0
A
1
A
2
A
3
D0-D8
CLK
Y
0
Y
1
Y
2
Y
3
RESET
4-BIT
CTR
SYSTEM
RESET
ADR1
ADR0
ADR2
V
CC
SHADD
SENBH
SENBL
DIN0-8
DIENB
CLK
CIN0-8
CIENB
DCM1
DCM0
RESET
ERASE
V
SS
COENB
COUT0-8
SUM0-25
HSP43891
DF0
FIGURE 5. HSP43891 30MHz, 16-TAP FIR FILTER CASCADE APPLICATION SCHEMATIC
HSP43891
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