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參數(shù)資料
| 型號： | HSP43881JC-30 |
| 廠商： | INTERSIL CORP |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | Digital Filter |
| 中文描述： | 8-BIT, DSP-DIGITAL FILTER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 148K |
| 代理商： | HSP43881JC-30 |
5
Functional Description
TheDigitalFilterProcessor(DF)iscomposedofeightfiltercells
cascaded together and an output stage for combining or
selectingfilte5rcelloutputs(SeeBlockDiagram).Eachfiltercell
contains a multiplier accumulator and several registers (Figure
1). Each 8-bit coefficient is multiplied by an 8-bit data sample,
with the result added to the 26-bit accumulator contents. The
coefficient output of each cell is cascaded to the coefficient
input of the next cell to its right.
DF Filter Cell
An 8-bit coefficient (CIN0-7) enters each cell through the C
register on the left and exits the cell on the right as signals
COUT0-7. With no decimation, the coefficient moves directly
from the C register to the output, and is valid on the clock
following its entrance. When decimation is selected the
coefficient exit is delayed by 1, 2 or 3 clocks by passing through
one or more decimation registers (D1, D2 or D3).
The combination of D registers through which the coefficient
passes is determined by the state of DCM0 and DCM1. The
output signals (COUT0-7) are connected to the CIN0-7 inputs
of the next cell to its right. The COENB input signal enables the
COUT0-7 outputs of the right most cell to the COUT-07 pins of
the device.
The C and D registers are enabled for loading by CIENB.
LoadingissynchronouswithCLKwhenCIENBislow.Notethat
DCM0-1
G2, L1
These two inputs determine the use of the internal decimation registers as follows:
DCM1
DCM0
Decimation Function
0
0
Decimation Registers not used.
0
1
One Decimation Register is used.
1
0
Two Decimation Registers are used.
1
1
Three Decimation Registers are used.
The coefficients pass from cell to cell at a rate determined by the number of decimation registers
used. When no decimation registers are used, coefficients move from cell to cell on each clock.
When one decimation register is used, coefficients move from cell to cell on every other clock, etc.
These signals are latched and delayed by one clock internal to the DF.
SUM0-25
J2, J5-8, J10,
K2, K5-11,
L-26, L8,
L10-11
O
These 26 three-state outputs are used to output the results of the internal filter cell computations.
Individual filter cell results or the result of the shift and add output stage can be output. If an individ-
ual filter cell result is to be output, the ADR0-2 signals select the filter cell result. The SHADD signal
determines whether the selected filter cell result or the output stage adder result is output. The sig-
nals SENBH and SENBL enable the most significant and least significant bits of the SUM0-25 result,
respectively. Both SENBH and SENBL may be enabled simultaneously if the system has a 26-bit or
larger bus. However, individual enables are provided to facilitate use with a 16-bit bus.
SENBH
K1
I
A low on this input enables result bits SUM16-25. A high on this input places these bits in their high
impedance state.
SENBL
E11
I
A low on this input enables result bits SUM0-15. A high on this input places these bits in their high
impedance state.
ADR0-2
G1, H1-2
I
These inputs select the one cell whose accumulator will be read through the output bus (SUM0-25)
or added to the output stage accumulator. They also determine which accumulator will be cleared
when ERASE is low. For selection of which accumulator to read through the output bus (SUM0-25)
or which to add to the output stage accumulator, these inputs are latched in the DF and delayed by
one clock internal to the device. If the ADR0-2 lines remain at the same address for more than one
clock, the output at SUM0-25 will not change to reflect any subsequent accumulator updates in the
addressed cell. Only the result available during the first clock, when ADR0-1 selects the cell, will be
output. This does not hinder normal operation since the ADR0-1 lines are changed sequentially.
This feature facilitates the interface with slow memories where the output is required to be fixed for
more than one clock.
SHADD
F3
I
The SHADD input controls the activation of the shift-and-add operation in the output stage. This
signal is latched in the DF and delayed by one clock internal to the device. A detailed explanation is
given in the DF Output Stage Section.
RESET
A4
I
A low on this input synchronously clears all the internal registers, except the cell accumulators. It
can be used with ERASE to also clear all the accumulators simultaneously. This signal is latched in
the DF and delayed by one clock internal to the DF.
ERASE
B4
I
A low on this input synchronously clears the cell accumulator selected by the ADR0-1 signals. If
RESET is also low simultaneously, all cell accumulators are cleared.
ALIGN PIN
C3
Used for aligning chip in socket or printed circuit board. Must be left as a no connect in circuit.
Pin Description
(Continued)
SYMBOL
PIN
NUMBER
TYPE
DESCRIPTION
HSP43881
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| HSP43891GC-20 | Digital Filter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HSP43881QM-20/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| HSP43881QM-25/883 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Digital Filter |
| HSP43891 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43891/883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
| HSP43891883 | 制造商:INTERSIL 制造商全稱:Intersil Corporation 功能描述:Digital Filter |
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