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參數(shù)資料
| 型號(hào)： | HS7B-1212RH-Q |
| 廠商： | INTERSIL CORP |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Radiation Hardened, Dual, High Speed Low Power, Video Closed Loop Buffer |
| 中文描述： | BUFFER AMPLIFIER, CDIP8 |
| 封裝： | SIDE BRAZED, CERAMIC, DIP-8 |
| 文件頁(yè)數(shù)： | 3/9頁(yè) |
| 文件大?。?/td> | 107K |
| 代理商： | HS7B-1212RH-Q |
3
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
An example of a good high frequency layout is the
Evaluation Board shown in Figure 3.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (R
S
) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the R
S
and C
L
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
R
S
and C
L
form a low pass network at the output, thus
limiting system bandwidth well below the amplifier bandwidth
of 350MHz. By decreasing R
S
as C
L
increases (as
illustrated in the curves), the maximum bandwidth is
obtained without sacrificing stability. In spite of this,
bandwidth decreases as the load capacitance increases.
Evaluation Board
The performance of the HS-1212RH may be evaluated using
the HA5023 Evaluation Board, slightly modified as follows:
1. Remove the two feedback resistors, and leave the
connections open.
2. a. For A
V
= +1 evaluation, remove the gain setting
resistors (R
1
), and leave pins 2 and 6 floating.
b. For A
V
= +2, replace the gain setting resistors (R
1
)
with 0
resistors to GND.
The modified schematic for amplifier 1, and the board layout
are shown in Figures 2 and 3.
To order evaluation boards (part number HA5023EVAL),
please contact your local sales office.
TABLE 1. UNITY GAIN PERFORMANCE FOR VARIOUS IMPLEMENTATIONS
APPROACH
PEAKING (dB)
BW (MHz)
±
0.1dB GAIN FLATNESS (MHz)
Remove -IN Pin
4.5
430
21
+R
S
= 620
0
220
27
+R
S
= 620
and Remove -IN Pin
0.5
215
15
Short +IN to -IN (e.g., Pins 2 and 3)
0.6
280
70
100pF Capacitor Between +IN and -IN
0.7
290
40
0
100
200
300
400
0
10
20
30
40
50
LOAD CAPACITANCE (pF)
S
)
A
V
= +2
150
250
350
50
A
V
= +1
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
5V
10
μ
F
0.1
μ
F
50
GND
GND
R
1
+
5V
0.1
μ
F
10
μ
F
50
IN
OUT
∞
(A
V
= +
1)
OR 0
(A
V
= +
2)
NOTE: R
1
=
FIGURE 2. MODIFIED EVALUATION BOARD SCHEMATIC
+
(NOTE)
1
2
3
4
8
7
6
5
HS-1212RH
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