參數(shù)資料
型號(hào)： HS1-565ARH-T
廠商： HARRIS SEMICONDUCTOR
元件分類： DAC
英文描述： Radiation Hardened High Speed, Monolithic Digital-to-Analog Converter
中文描述： PARALLEL, WORD INPUT LOADING, 0.35 us SETTLING TIME, 12-BIT DAC, CDIP24
文件頁(yè)數(shù)： 3/7頁(yè)
文件大?。?/td> 169K
代理商： HS1-565ARH-T
3
Burn-In Bias Circuit
NOTES:
D1 = D2 = D3 = IN4002 or Equivalent
F0 to F11:
VIH = 5.0V
±
0.5V
VIL = 0.0V
±
0.5V
F0 = 100kHz
±
10% (50% Duty Cycle)
F1 = F0/2
F2 = F0/4
F3 = F0/8
F4 = F0/16
F5 = F0/32
F6 = F0/64
F7 = F0/128
F8 = F0/256
F9 = F0/512
F10 = F0/1024
F11 = F0/2048
Radiation Bias Circuit
NOTE: Power Supply Levels are ±0.5V
Definitions of Specifications
Digital Inputs
The HS-565BRH accepts digital input codes in binary format
and may be user connected for any one of three binary
codes. Straight binary, Two’s Complement (see note below),
or Offset Binary, (See Operating Instructions).
Accuracy
Nonlinearity
- Nonlinearity of a D/A converter is an
important measure of its accuracy. It describes the deviation
from an ideal straight line transfer curve drawn between zero
(all bits OFF) and full scale (all bits ON).
Differential Nonlinearity
- For a D/A converter, it is the
difference between the actual output voltage change and the
ideal (1 LSB) voltage change for a one bit change in code. A
Differential Nonlinearity of
±
1 LSB or less guarantees
monotonicity; i.e., the output always increases and never
decreases for an increasing input.
Settling Time
Settling time is the time required for the output to settle to
within the specified error band for any input code transition.
It is usually specified for a full scale or major carry transition,
settling to within 0.50
LSB of final value.
Drift
Gain Drift
- The change in full scale analog output over the
specified temperature range expressed in parts per million of
full scale range per
o
C (ppm of FSR/
o
C). Gain error is
measured with respect to 25
o
C at high (TH) and low (TL)
temperatures. Gain drift is calculated for both high (TH -
25
o
C) and low ranges (25
o
C - TL) by dividing the gain error by
the respective change in temperature. The specification is the
larger of the two representing worst case drift.
Offset Drift
- The change in analog output with all bits OFF
over the specified temperature range expressed in parts per
million of full scale range per
o
C (ppm of FSR/
o
C). Offset
error is measured with respect to 25
o
C at high (TH) and low
(TL) temperatures. Offset drift is calculated for both high (TH
- 25
o
C) and low (25
o
C - TL) ranges by dividing the offset
error by the respective change in temperature. The
specification given is the larger of the two, representing
worst case drift.
C3
D3
+10V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
C1
D1
+15V
C2
D2
-15V
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
F11
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
+15V
1
4
5
8
9
10
11
12
16
17
18
19
20
21
22
23
24
15
14
13
2
3
6
7
NC
NC
VCC
REF GND
REF OUT
REF IN
-VEE
BIP OFF
OUT
10V SPAN
20V SPAN
PWR GND
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 10
BIT 11
BIT 12
-15V
+10V
+5V
DIGITAL
INPUT
ANALOG OUTPUT
STRAIGHT
BINARY
OFFSET
BINARY
(NOTE)
TWO’S
COMPLEMENT
MSB...LSB
000....000
Zero
0.50
FS
-FS (Full Scale)
Zero
100....000
Zero
-FS
111....111
+FS - 1LSB
0.50
FS - 1LSB
+FS - 1LSB
Zero - 1LSB
011....111
Zero - 1LSB
+FS - 1LSB
NOTE: Invert MSB with external inverter to obtain Two’s
Complement Coding
HS-565BRH
相關(guān)PDF資料
PDF描述
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