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參數(shù)資料
| 型號： | HPLL-8001 |
| 英文描述： | PLL Frequency Synthesizer (92K in pdf) |
| 中文描述： | 鎖相環(huán)頻率合成器（的92K，PDF格式） |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 91K |
| 代理商： | HPLL-8001 |
11
Functional Description
Frequency Divider
The division ratio can be
calculated as follows:
FVCO = ( N x P + A) / R x
FREF
where,
FVCO
: Output frequency of the
external VCO
FREF
: Reference oscillator
frequency
N
: divide ratio of the N counter
3
≤
N
≤
16380
A
: divide ratio of the A counter
0
≤
A
≤
127
R
: divide ratio of the R counter
3
≤
R
≤
65535
P
: divide ratio of the external dual
modulus prescaler
Phase Detector and
Charge Pump
The phase detector is a digital,
edge-sensitive comparator with
UP and DOWN outputs. Both
outputs can be monitored at the
outputs PO1 and PO2. The phase
detector drives a charge pump,
which is a switch with a tristate
state. The output current can be
programmed in 8 steps between
0.15 mA and 1.69 mA (VDD = 4.5
to 5.5 V) with a reference current
of 100
μ
A.
If VCOI < REFI, the charge pump
delivers a positive current to the
external loop filter. If VCOI >
REFI, the charge pump sinks a
negative current from the external
loop filter. The charge pump
output can be inverted by
software.
Anti-backlash pulses are gener-
ated to extend the very short
phase difference between VCOI
and REFI.
Programming
The HPLL-8001 can be
programmed through a 3-wire
interface. Four different words
can be sent over this interface to
program the internal registers. All
four words consists of a 2-bit
address and a variable data
portion. When EN=L, the data is
transferred. It is loaded into the
internal registers at the rising
edge of EN. The last two bits
which are transferred, form the
address bits. When EN=H, the
input signals, CLK and DATA, are
internally disabled.
The Status registers contains all
status information.
The reduced Status register is a
reduced version of the status
register.
The N and A counter register and
the R counter register contain the
applicable counter values.
The programming of the device
must start with the loading of the
status register.
The N, A and R counters can be
loaded synchronously or asyn-
chronously. If synchronous
loading is selected, all counters
are loaded when they reach the
value zero. As a result, the phase
difference between the divided
VCOI and REFI signal remains the
same.
For synchronous loading the
following order of programming
must be followed:
1) programming of synchronous
loading using the status
register
2) programming of the R counter
3) programming of the N, A
counters
The rising edge of EN enables the
synchronous loading of all
counters at their zero value.
Standby
The HPLL-8001 has two standby
modes.
In standby mode 1, the whole
device is powered down with the
exception of the serial interface.
In standby mode 2, the serial
interface and the input amplifiers
are active. All other parts are
powered down.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HPLL-8001-TR1 | Rack/panel connectors, Crimping type; HRS No: 221-0107-1 00; Connector Type: Wire; Contact Gender: Male; Applicable Cable: Conductor AWG#24 to #28; Termination Style: Crimping; Current Rating(Amps)(Max.): 3; Mating/Unmating Cycles: 1000; Contact Mating Area Plating: Gold; General Description: Crimp contact; For Signal |
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