K ey Specifications
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486DX, DX2, DX4
486DX4
486SX
486SX
486SL Enhanced
486SL Enhanced
487SX
OverDrive
Pentium
Notes:
(1) HP E5344A CQFP/PQFP adapter required
(2) Emulation Technologyadapter required
168-pin PGA
208-pin PQFP (1)
168-pin PGA
196-pin PQFP (2)
168-pin PGA
208-pin PQFP (1)
169-pin PGA
235-pin PGA
Supply Voltage
The HP E2411C supports both
3.3V and 5V versions of the
Intel486 family of processors.
Clock F requency
Processor core clock frequency to
100 MHz
Minimum bus clock frequency
5 MHz
Maximum bus clock frequency
50 MHz
Capabilities
State per clock mode—provides a
complete display of all bus activi-
ty, including wait states, idle
states, and cache invalidation
cycles.
State per transfer mode — filters
out wait and idle states , provid-
ing an easier to read display.
Timing mode — timing analysis is
supported up to 500 MHz.
Channel-to-channel skew is 1 ns.
The preprocessor allows you to
improve trace readability by con-
trolling the amount of informa-
tion being sent to the analyzer.
For example, you can configure
the preprocessor to filter out
cache invalidation cycles from
the analyzer. For DMA transfers
you can configure the preproces-
sor to send all DMA cycles, to
send just one cycle which indi-
cates a DMA transfer occurred,
or to send no DMA cycles to the
analyzer.
The following types of instruc-
tions can be selected to be
displayed or suppressed:
unexecuted prefetches, jumps,
calls/returns, and other instruc-
tions. In addition, the following
operations can be displayed or
suppressed: memory read/writes,
I/O read/writes, special cycles,
and interrupt acknowledge
cycles. Also, FPU instructions
are decoded in the display.
L ogic Analyzer
Configurations
Includes all Intel486 processors
listed above
HP 16511B
HP 16540A, D with two
HP 16541A, D cards
HP 16550A (one card required)
HP 16554A (two cards required)
HP 16555A (two cards required)
HP 16556A (two cards required)
HP 1660-series
Number of Probes R equired
Five, sixteen-channel probes are
required for complete state dis-
assembly. Two additional pods
can be used to monitor AHOLD,
INTR, RESET, FLUSH#, BREQ,
HOLD, A20M#, PLOCK, PWT,
ADS#, RDY#, BRDY#, CACHE#,
BLEN#, HITM#, HIT#, UP#,
BRDYC#, INV, R/S#, PRDY,
NMI, INIT, IGNNE#, FERR#,
ETRDY#, ETADS#, SMIACT#,
SMI#, PCHK#, EWBE#, and
WB/WT#.
Termination Adapters
R equired
None. All pods are terminated
on the preprocessor.
Emulation Technology, Inc.
2344 Walsh Ave. Bldg F
Santa Clara, CA 95051
Ph. 408-982-0660
Fax: 408-982-0664
Maximum bus clock rate is 33 MHz
2