參數(shù)資料
型號： HPC46003
廠商： National Semiconductor Corporation
英文描述： High-Performance microControllers
中文描述： 高性能微控制器
文件頁數(shù)： 33/36頁
文件大?。?/td> 467K
代理商： HPC46003
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and
Figure 1 thru Figure 5 )VCC e 50V g10% unless otherwise specified TA e 0 Cto a70 C for
HPC46083HPC46003 b40 Cto a85 C for HPC36083HPC36003 b40 Cto a105 C for HPC26083HPC26003 b55 Cto
a
125 C for HPC16083HPC16003 (Continued)
Symbol and Formula
Parameter
Min
Max
Units
Notes
tDC1ALER
Delay from CKI Rising Edge to ALE Rising Edge
0
35
ns
(Notes 1 2)
tDC1ALEF
Delay from CKI Rising Edge to ALE Falling Edge
0
35
ns
(Notes 1 2)
tDC2ALER e
tC a 20
Delay from CK2 Rising Edge to ALE Rising Edge
37
ns
(Note 2)
tDC2ALEF e
tC a 20
Delay from CK2 Falling Edge to ALE Falling Edge
37
ns
(Note 2)
tLL e
tC b 9
ALE Pulse Width
24
ns
tST e
tC b 7
Setup of Address Valid before ALE Falling Edge
9
ns
tVP e
tC b 5
Hold of Address Valid after ALE Falling Edge
11
ns
tARR e
tC b 5
ALE Falling Edge to RD Falling Edge
12
ns
tACC e tC a WS b 32
Data Input Valid after Address Output Valid
100
ns
(Note 6)
tRD e
tC a WS b 39
Data Input Valid after RD Falling Edge
60
ns
tRW e
tC a WS b 14
RD Pulse Width
85
ns
tDR e
tC b 15
Hold of Data Input Valid after RD Rising Edge
0
35
ns
tRDA e tC b 15
Bus Enable after RD Rising Edge
51
ns
tARW e
tC b 5
ALE Falling Edge to WR Falling Edge
28
ns
tWW e
tC a WS b 15
WR Pulse Width
101
ns
tV e
tC a WS b 5
Data Output Valid before WR Rising Edge
94
ns
tHW e
tC b 10
Hold of Data Valid after WR Rising Edge
7
ns
tDAR e
tC a WS b 50
Falling Edge of ALE to Falling Edge of RDY
33
ns
tRWP e tC
RDY Pulse Width
66
ns
Address
Cycles
Read
Cycles
Write
Cycles
Ready
Input
Note
CL e 40 pF
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO wih rise and fall
times (tCKIR and tCKIL) on CKI input less than 25 ns
Note 2
Do not design with these parameters unless CKI is driven with an active signal When using a passive crystal circuit its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed If HLD falling
edge occurs later tHAE as long as (3tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction cycles its wait states and ready input
Note 4
WS tWAIT c (number of pre-programmed wait states) Minimum and maximum values are calculated from maximum operating frequency tC e 30 MHz
with one wait state programmed
Note 5
Due to emulation restrictionsactual limits will be better
Note 6
This is guaranteed by design and not tested
CKI Input Signal Characteristics
RiseFall Time
TLDD8801 – 35
Duty Cycle
TLDD8801 – 36
FIGURE 1 CKI Input Signal
TLDD8801 – 38
FIGURE 2 Input and Output for AC Tests
Note
AC testing inputs are driven at VIH for a logic ‘‘1’’ and VIL for a logic ‘‘0’’ Output timing measurements are made at 20V for a logic ‘‘1’’ and 08V for a logic
‘‘0’’
6
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