參數(shù)資料
型號： HPC36400EV
廠商： National Semiconductor Corporation
英文描述： High-Performance Communications MicroController
中文描述： 高性能通信微控制器
文件頁數(shù)： 23/30頁
文件大?。?/td> 362K
代理商： HPC36400EV
AC Electrical Characteristics
(see Notes 1 and 4 and
Figures 1 thru 5 ) VCC e 5V g10% TA e 0 Cto a70 C for HPC46400E b40 Cto a85 C for
HPC36400E
Symbol and Formula
Parameter and Notes
Min
Max
Units
Note
fC
Operating Frequency
2
20
MHz
tC1 e 1fC
Operating Period
50
500
ns
tCKIH
CKI Rise Time
225
ns
tCKIL
CKI Fall Time
225
ns
tC e 2fC
CPU or DMA Timing Cycle
100
ns
tWAIT e tC
CPU or DMA Wait State Period
100
ns
tDC1C2R
Delay of CK2 Rising Edge after
0
55
ns
(Note 2)
CKI Falling Edge
tDC1C2F
Delay of CK2 Falling Edge after
0
55
ns
(Note 2)
CKI Falling Edge
fU e fC 8
External UART Clock Input Frequency
25
MHz
fMW
External MICROWIREPLUS
125
MHz
Clock Input Frequency
tHCK e 4tC1 a 14
HDLC Clock Input Period
214
ns
fXIN e fC 22
External Timer Input Frequency
091
kHz
tXIN e tC
Pulse Width for Timer Inputs
100
ns
tUWS
MICROWIRE Setup Time
Master
100
ns
Slave
20
ns
tUWH
MICROWIRE Hold Time
Master
20
ns
Slave
50
ns
tUWV
MICROWIRE Output Valid Time
Master
50
ns
Slave
150
ns
tSALE e
tC a 40
HLD Falling Edge before ALE Rising Edge
115
ns
tHWP e
tC a 35
HLD Pulse Width
110
ns
tHAE e
tC a 100
HLDA Falling Edge after HLD Falling Edge
175
ns
(Note 3)
tHAD e
tC a 85
HLDA Rising Edge after HLD Rising Edge
210
ns
tBF
Bus Float after HLDA Falling Edge
66
ns
tBE e tC b 66
Bus Enable after HLDA Rising Edge
34
ns
Clocks
Timers
MICROWIRE
PLUS
External
Hold
Note 1
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO Spec’d tC1R tC1F
and CKI duty cycle limits are not tested but are guaranteed functional by design Keep in mind that when SLOW mode is selected fC (Operating Frequency) will be
the external frequency divided by 4 and that value should be used in all formulas relating to the AC Characteristics
Note 2
Do not design with this parameter unless CKI is driven with an active signal and SLOW mode is not selected When using a passive crystal circuit its
stability is not guaranteed if either CKI or CKO is connected to any external logic other than the passive components of the crystal circuit
Note 3
tHAE is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed If HLD
falling edge occurs later tHAE as long as (3 tC a 4WS a 72 tC a 100) may occur depending on the following CPU instruction or DMA cycle its wait states and
ready input
Note 4
WS (tWAIT) c (number of preprogrammed wait states) Minimum and maximum values are calculated at maximum operating frequency fC e 20 MHz with
one wait state preprogrammed These values are guaranteed with AC loading of 100 pF on Port A 50 pF on CK2 80 pF on other outputs and DC loading of the
pin’s DC spec non CMOS IOL or IOH
3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HPC36400EV2 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
HPC36400EV20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
HPC36400EVHG2 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
HPC36400EVHG20 制造商:NSC 制造商全稱:National Semiconductor 功能描述:High-Performance Communications MicroController
HPC36400L20 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller
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