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參數(shù)資料
| 型號： | HPC26064 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microController |
| 中文描述： | 高性能微控制器 |
| 文件頁數(shù)： | 5/37頁 |
| 文件大?。?/td> | 487K |
| 代理商： | HPC26064 |
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30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 through Figure 5.) V
CC
e
5V
g
10% unless otherwise specified, T
A
e
0
§
C to
a
70
§
C for
HPC46064/46004,
b
40
§
C to
a
85
§
C for HPC36064/36004,
b
40
§
C to
a
105
§
C for HPC26064/26004,
b
55
§
C to
a
125
§
C for
HPC16064/16004
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
C
t
C1
e
1/f
C
CKI Operating Frequency
2
30
MHz
CKI Clock Period
33
500
ns
t
CKIH
CKI High Time
15
ns
t
CKIL
t
C
e
2/f
C
t
WAIT
e
t
C
CKI Low Time
16.6
ns
CPU Timing Cycle
66
ns
CPU Wait State Period
66
ns
t
DC1C2R
Delay of CK2 Rising Edge after CKI Falling Edge
0
55
ns
(Note 2)
t
DC1C2F
f
U
e
f
C
/8
f
MW
f
XIN
e
f
C
/22
t
XIN
e
t
C
Delay of CK2 Falling Edge after CKI Falling Edge
0
55
ns
(Note 2)
External UART Clock Input Frequency
External MICROWIRE/PLUS Clock Input Frequency
3.75
*
1.875
MHz
MHz
External Timer Input Frequency
Pulse Width for Timer Inputs
1.36
MHz
ns
66
t
UWS
MICROWIRE Setup Time
Master
Slave
100
20
ns
t
UWH
MICROWIRE Hold Time
Master
Slave
20
50
ns
t
UWV
MICROWIRE Output Valid Time
Master
Slave
50
150
ns
t
SALE
e
*/4
t
C
a
40
t
HWP
e
t
C
a
10
t
HAE
e
t
C
a
85
t
HAD
e
*/4
t
C
a
85
t
BF
e
(/2
t
C
a
66
t
BE
e
(/2
t
C
a
66
HLD Falling Edge before ALE Rising Edge
90
ns
HLD Pulse Width
76
ns
HLDA Falling Edge after HLD Falling Edge
151
ns
(Note 3)
HLDA Rising Edge after HLD Rising Edge
135
ns
Bus Float after HLDA Falling Edge
99
ns
(Note 5)
Bus Enable after HLDA Rising Edge
99
ns
(Note 5)
t
UAS
Address Setup Time to Falling Edge of URD
10
ns
t
UAH
Address Hold Time from Rising Edge of URD
10
ns
t
RPW
URD Pulse Width
100
ns
t
OE
URD Falling Edge to Output Data Valid
0
60
ns
t
OD
Rising Edge of URD to Output Data Invalid
5
35
ns
(Note 6)
t
DRDY
RDRDY Delay from Rising Edge of URD
70
ns
t
WDW
UWR Pulse Width
40
ns
t
UDS
Input Data Valid before Rising Edge of UWR
10
ns
t
UDH
Input Data Hold after Rising Edge of UWR
20
ns
t
A
WRRDY Delay from Rising Edge of UWR
70
ns
C
T
M
E
U
*
This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
5
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HPC36004 | High-Performance microController |
| HPC36064 | High-Performance microController |
| HPC46064 | High-Performance microController |
| HPC3130PBK | PCI Bus Interface/Controller |
| HPC3130PBM | PCI Bus Interface/Controller |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HPC26064XXX/E30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| HPC26064XXX/EL20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| HPC26064XXX/EL30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| HPC26064XXX/L30 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
| HPC26064XXX/T20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:16-Bit Microcontroller |
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