20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figure 1 thru Figure 5) V
CC
e
5.0V
g
10% unless otherwise specified, T
A
e
0
§
C to
a
70
§
C for
HPC46083/HPC46003,
b
40
§
C to
a
85
§
C for HPC36083/HPC36003,
b
40
§
C to
a
105
§
C for HPC26083/HPC26003,
b
55
§
C to
a
125
§
C for HPC16083/HPC16003 (Continued)
Symbol and Formula
Parameter
Min
Max
Units
Note
t
DC1ALER
Delay from CKI Rising
Edge to ALE Rising Edge
0
35
ns
(Notes 1, 2)
t
DC1ALEF
Delay from CKI Rising
Edge to ALE Falling Edge
0
35
ns
(Notes 1, 2)
t
DC2ALER
e
(/4
tC
a
20
Delay from CK2 Rising
Edge to ALE Rising Edge
45
ns
(Note 2)
t
DC2ALEF
e
(/4
tC
a
20
Delay from CK2 Rising
Edge to ALE Rising Edge
45
ns
(Note 2)
t
LL
e
(/2
t
C
b
9
ALE Pulse Width
41
ns
t
ST
e
(/4
t
C
b
7
Setup of Address Valid
before ALE Falling Edge
18
ns
t
VP
e
(/4
t
C
b
5
Hold of Address Valid
after ALE Falling Edge
20
ns
t
ARR
e
(/4
t
C
b
5
ALE Falling Edge to RD Falling Edge
20
ns
t
ACC
e
t
C
a
WS
b
55
Data Input Valid after
Address Output Valid
145
ns
(Note 6)
t
RD
e
(/2
t
C
a
WS
b
65
Data Input Valid after
RD Falling Edge
95
ns
t
RW
e
(/2
t
C
a
WS
b
10
RD Pulse Width
140
ns
t
DR
e
*/4
t
C
b
15
Hold of Data Input Valid
after RD Rising Edge
0
60
ns
t
RDA
e
t
C
b
15
Bus Enable after RD Rising Edge
85
ns
t
ARW
e
(/2
t
C
b
5
ALE Falling Edge to
WR Falling Edge
45
ns
t
WW
e
*/4
t
C
a
WS
b
15
WR Pulse Width
160
ns
t
V
e
(/2
t
C
a
WS
b
5
Data Output Valid before
WR Rising Edge
145
ns
t
HW
e
(/4
t
C
b
5
Hold of Data Valid after
WR Rising Edge
20
ns
t
DAR
e
(/4
t
C
a
WS
b
50
Falling Edge of ALE
to Falling Edge of RDY
75
ns
t
RWP
e
t
C
RDY Pulse Width
100
ns
A
R
W
R
I
Note:
C
L
e
40 pF.
Note 1:
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and T
CKIL
) on CKI input less than 2.5 ns.
Note 2:
Do not design with these parameters unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3:
t
HAE
is spec’d for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed. If HLD falling
edge occurs later, t
HAE
as long as (3t
C
a
4WS
a
72 t
C
a
100) may occur depending on the following CPU instruction cycles, its wait state and ready input.
Note 4:
WS (t
WAIT
) x (number of preprogrammed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
C
e
20 MHz, with
one wait programmed.
Note 5:
Due to emulation restrictionsDactual limits will be better.
Note 6:
This is guaranteed by design and not tested.
4