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參數(shù)資料
| 型號(hào)： | HPC16083 |
| 廠(chǎng)商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microControllers |
| 中文描述： | 高性能微控制器 |
| 文件頁(yè)數(shù)： | 9/36頁(yè) |
| 文件大?。?/td> | 467K |
| 代理商： | HPC16083 |
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The following is the Military 883 Electrical Specification for HPC16083 and HPC16003. For latest information on RETS 16083X
contact NSC local sales office.
DC Electrical Specifications
Test Conditions V
CC
e
5V
g
10% (Unless Otherwise Specified) (Note 1)
Symbol
Parameter
Conditions
SBGRP 1
a
25
§
C
SBGRP 2
a
125
§
C
SBGRP 3
b
55
§
C
Units
Notes
Min
Max
Min
Max
Min
Max
V
IH1
Logical ‘‘1’’ Input
Voltage
RESET, NMI, CKI and WO
B
10
–B
13
, B
15
All Inputs except Port A
0.9
(V
CC
)
0.7
(V
CC
)
4.65
3.95
0.9
(V
CC
)
0.7
(V
CC
)
4.65
3.95
0.9
(V
CC
)
0.7
(V
CC
)
4.65
3.95
V
V
IH2
V
V
IH3
Port A, V
CC
e
5.5V
Port A, V
CC
e
4.5V
RESET, NMI, CKI and WO
V
V
(Note 2)
(Note 2)
V
IL1
Logical ‘‘0’’ Input
Voltage
0.1
(V
CC
)
0.2
(V
CC
)
0.7
0.5
0.1
(V
CC
)
0.2
(V
CC
)
0.7
0.5
0.1
(V
CC
)
0.2
(V
CC
)
0.7
0.5
V
V
IL2
All Inputs except Port A
V
V
IL3
Port A, V
CC
e
5.5V
Port A, V
CC
e
4.5V
I
OH
e b
7 mA (A
0
–A
15
,
B
10
–B
, B
15
, CK2)
I
OH3
e b
1.6 mA (B
0
–B
9
, B
13
–B
14
,
P
0
–P
), WO (Open Drain)
I
OH
e b
6 mA (ST1, ST2)
I
OH
e b
1 mA (A
0
–A
15
, B
10
–B
12
, B
15
)
When Used as an External
Address/Data Bus
V
V
(Note 3)
(Note 3)
V
OH2
Logical ‘‘1’’ Output
Voltage
2.4
2.4
2.4
V
V
OH3
2.4
2.4
2.4
V
V
OH4
V
OH5
2.4
2.4
2.4
V
2.4
2.4
2.4
V
V
OL2
V
OL3
Logical ‘‘0’’ Output
Voltage
I
OL
e
3 mA (CK2, A
0
–A
15
, B
10
-B
12
, B
15
)
I
OL
e
0.5 mA (B
0
–B
9
, B
13
-B
14
, P
0
–P
3
WO (Open Drain)
I
OL
e
1.6 mA (ST1, ST2)
I
OL
e
3 mA (A
0
–A
15
, B
10
–B
12
, B
15
)
When Used as an External
Address/Data Bus
0.4
0.4
0.4
V
0.4
0.4
0.4
V
V
OL4
V
OL5
0.4
0.4
0.4
V
0.4
0.4
0.4
V
I
OZ
TRI-STATE Leakage V
SS
s
V
IN
s
V
CC
(WO, Port A,
Port B), V
CC
e
5.5V
Input Leakage
V
SS
s
V
IN
s
V
CC
, V
CC
e
5.5V
Current
(I
1
–I
6
, D
0
–D
7
, CKI,
RESET, EXM, EI)
g
5
g
5
g
5
m
A
I
LI1
g
2
g
2
g
2
m
A
(Note 7)
I
LI2
Input Pullup Current
V
IN
e
0 (I
0
, I
7
, RDY/HLD,
EXUI), V
CC
e
5.5V
V
IN
e
V
CC
, Port B
12
,
V
CC
e
5.5V
Test Duration is 10 ms
b
50
b
3
b
50
b
3
b
50
b
3
m
A
(Note 7)
I
LI3
Port B
12
Pulldown
during Reset
1
7
1
7
1
7
mA
VRAM
RAM Keep Alive
Voltage
2.5
2.5
2.5
V
I
CC1
Supply Current
Dynamic
F
IN
e
20 MHz, RESET
e
V
SS
,
I
OH
e
0 mA, I
OL
e
0 mA, V
CC
e
5.5V
F
IN
e
20 MHz, External Clock
NMI
e
V
CC
f
test
e
1.0 MHz,
I/O Pin to Ground
55
55
55
mA
I
CC2
I
CC
CI/O
Idle Mode Current
3.5
3.5
3.5
mA
Halt Mode Current
2
2
2
mA
Input/Output
Capacitance
20
pF
(Note 4)
SBGRP4
CI
Input Capacitance
f
test
e
1.0 MHz,
Input Pin to Ground
10
pF
(Note 4)
Note 1:
Electrical end point testing (when required) for Groups C & D shall consist only of subgroups 1, 2, 9 and 10.
Note 2:
Port A V
IH
test limit includes 700 mV offset caused by output loads being on during Data Drive Time.
Note 3:
Port A V
IL
test limit includes 400 mV offset caused by output loads being on during Data Drive Time.
Note 4:
Verified at initial qual only.
Note 7:
Future revisions of this device will not have pullups on pins I
0
, I
7
which will be tested to I
LI1
conditions.
9
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