參數(shù)資料
型號(hào)： HPC-DEV-SYS4-E
廠商： National Semiconductor Corporation
英文描述： Category 5e Cable Assembly; Connector Type A:RJ45 Plug; Connector Type B:RJ45 Plug; Cable Length:3m; Color:Black; Features:IP20 Rated RoHS Compliant: Yes
中文描述： 高性能微控制器/數(shù)
文件頁數(shù)： 7/39頁
文件大?。?/td> 430K
代理商： HPC-DEV-SYS4-E
30 MHz
(Continued)
AC Electrical Characteristics
(See Notes 1 and 4 andFigure 1 throughFigure 5 .) V
CC
e
5V
g
10%, T
A
e
0
§
C to
a
70
§
C for HPC46164/HPC46104,
b
55
§
C
to
a
125
§
C for HPC16164/HPC16104.
Symbol and Formula
Parameter
Min
Max
Units
Notes
t
DC1ALER
Delay from CKI Rising Edge to
ALE Rising Edge
0
35
ns
(Notes 1, 2)
t
DC1ALEF
Delay from CKI Rising Edge to
ALE Falling Edge
0
35
ns
(Notes 1, 2)
t
DC2ALER
e
(/4
t
C
a
20
Delay from CK2 Rising Edge to
ALE Rising Edge
37
ns
(Note 2)
t
DC2ALEF
e
(/4
t
C
a
20
Delay from CK2 Falling Edge to
ALE Falling Edge
37
ns
(Note 2)
t
LL
e
(/2
t
C
b
9
t
ST
e
(/4
t
C
b
7
ALE Pulse Width
24
ns
Setup of Address Valid before
ALE Falling Edge
9
ns
t
VP
e
(/4
t
C
b
5
Hold of Address Valid after
ALE Falling Edge
11
ns
t
ARR
e
(/4
t
C
b
5
t
ACC
e
t
C
a
WS
b
32
t
RD
e
(/2
t
C
a
WS
b
39
t
RW
e
(/2
t
C
a
WS
b
14
t
DR
e
*/4
t
C
b
15
ALE Falling Edge to RD Falling Edge
11
ns
Data Input Valid after Address Output Valid
100
ns
(Note 6)
Data Input Valid after RD Falling Edge
60
ns
RD Pulse Width
85
ns
Hold of Data Input Valid after
RD Rising Edge
0
35
ns
t
RDA
e
t
C
b
15
t
ARW
e
(/2
t
C
b
5
t
WW
e
*/4
t
C
a
WS
b
15
t
V
e
(/2
t
C
a
WS
b
5
t
HW
e
(/4
t
C
b
10
t
DAR
e
(/4
t
C
a
WS
b
50
Bus Enable after RD Rising Edge
51
ns
ALE Falling Edge to WR Falling Edge
28
ns
WR Pulse Width
101
ns
Data Output Valid before WR Rising Edge
94
ns
Hold of Data Valid after WR Rising Edge
7
ns
Falling Edge of ALE to
Falling Edge of RDY
33
ns
t
RWP
e
t
C
RDY Pulse Width
66
ns
A
R
W
R
I
Note:
C
L
e
40 pF.
Note 1:
These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t
CKIR
and t
CKIL
) on CKI input less than 2.5 ns.
Note 2:
Do not design with these parameters unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either
CKI or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3:
t
HAE
is specified for case with HLD falling edge occurring at the latest time it can be accepted during the present CPU cycle being executed. If HLD falling
edge occurs later, t
HAE
may be as long as (3 t
C
a
4WS
a
72 t
C
a
100) may occur depending on the following CPU instruction cycles, its wait states and ready
input.
Note 4:
WS (t
WAIT
)
c
(number of preprogrammed wait states). Minimum and maximum values are calculated at maximum operating frequency, t
C
e
30 MHz, with
one wait state programmed.
Note 5:
Due to emulation restrictionsDactual limits will be better.
Note 6:
This is guaranteed by design and not tested.
7
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