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參數(shù)資料
| 型號(hào)： | HPC-DEV-SUNDB |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | High-Performance microController with A/D |
| 中文描述： | 高性能微控制器/數(shù) |
| 文件頁數(shù)： | 27/39頁 |
| 文件大?。?/td> | 430K |
| 代理商： | HPC-DEV-SUNDB |
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A/D Converter
(Continued)
TABLE IV. A/D Operating Modes
Mode 0
Single-ended, single channel, single result
register, one-shot (default value on power-up)
Mode 1
Single-ended, single channel, single result
register, continuous
Mode 2
Single-ended, single channel, multiple result
registers, stop after 8
Mode 3
Single-ended, multiple channel, multiple result
registers, continuous
Mode 4
Differential, single channel-pair, single result
register-pair, one-shot
Mode 5
Differential, single channel-pair, single result
register-pair, continuous
Mode 6
Differential, single channel-pair, multiple result
register-pairs, stop after 4 pairs
Mode 7
Differential, multiple channel-pair, multiple
result register-pairs, continuous
Mode 8
Single-ended, single channel, single result
register, one-shot (default value on power-
up), quiet address/data bus
Mode C
Differential, single channel-pair, single result
register-pair, one-shot, quiet address/data bus
Source impedances greater than 1 k
X
on the analog input
lines will adversely affect internal RC charging time during
input sampling. As shown inFigure 27, the analog switch to
the capacitor array is closed only during the 2 A/D cycle
sample time. Large source impedances on the analog in-
puts may result in the capacitor array not being charged to
the correct voltage levels, causing scale errors.
If large source resistance is necessary, the recommended
solution is to slow down the A/D clock speed in proportion
to the source resistance. The A/D converter may be operat-
ed at the maximum speed for R
S
less than 1 k
X
. For R
S
greater than 1 k
X
, A/D clock speed needs to be reduced.
For example, with R
S
e
2 k
X
, the A/D converter may be
operated at half the maximum speed. A/D converter clock
speed may be slowed down by either increasing the A/D
prescaler divide-by or decreasing the CKI clock frequency.
The A/D clock speed may be reduced to its minimum fre-
quency of 100 kHz.
Universal Peripheral Interface
The
Universal
Peripheral
HPC46164 to be used as an intelligent peripheral to another
processor. The UPI could thus be used to tightly link two
HPC46164’s and set up systems with very high data ex-
change rates. Another area of application could be where
an HPC46164 is programmed as an intelligent peripheral to
a host system such as the Series 32000
é
microprocessor.
Figure 28 illustrates how an HPC46164 could be used as an
intelligent peripherial for a Series 32000-based application.
Interface
(UPI)
allows
the
The interface consists of a Data Bus (port A), a Read Strobe
(URD), a Write Strobe (UWR), a Read Ready Line (RDRDY),
a Write Ready Line (WRRDY) and one Address Input (UA0).
The data bus can be either eight or sixteen bits wide.
The URD and UWR inputs may be used to interrupt the
HPC46164. The RDRDY and WRRDY outputs may be used
to interrupt the host processor.
The UPI contains an Input Buffer (IBUF), an Output Buffer
(OBUF) and a Control Register (UPIC). In the UPI mode,
port A on the HPC46164 is the data bus. UPI can only be
used if the HPC46164 is in the Single-Chip mode.
TL/DD/9682–30
FIGURE 28. HPC46164 as a Peripheral: (UPI Interface to Series 32000 Application)
27
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