參數(shù)資料
型號(hào)： HN58X2532FPI
英文描述： HN58X2532I/HN58X2564I Datasheet
中文描述： HN58X2532I/HN58X2564I數(shù)據(jù)表
文件頁(yè)數(shù)： 8/20頁(yè)
文件大小： 59K
代理商： HN58X2532FPI
HN58X2408/HN58X2416/HN58X2432/HN58X2464FPIAG
8
Device Address
(A0, A1, A2)
Eight devices can be wired for one common data bus line as maximum. Device address pins are used to
distinguish each device and device address pins should be connected to V
CC
or V
SS
. When device address
code provided from SDA pin matches corresponding hard-wired device address pins A0 to A2, that one
device can be activated. As for 8k to 16k EEPROM, whole or some device address pins don't need to be
fixed since device address code provided from the SDA pin is used as memory address signal.
Pin Connections for A0 to A2
Pin connection
Memory size
Max connect
number
A2
A1
A0
Notes
8k bit
2
V
CC
/V
SS
*
1
×
*
2
×
×
×
Use A0, A1 for memory address a8 and a9
16k bit
1
×
Use A0, A1, A2 for memory address a8, a9 and
a10
32k bit
8
V
CC
/V
SS
V
CC
/V
SS
V
CC
/V
SS
V
CC
/V
SS
V
CC
/V
SS
V
CC
/V
SS
64k bit
Notes: 1. “V
CC
/V
SS
” means that device address pin should be connected to V
CC
or V
SS
.
2.
×
= Don’t care (Open is also approval.)
8
Write Protect
(WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in
the following table. When the WP is low, write operation for all memory arrays are allowed. The read
operation is always activated irrespective of the WP pin status. WP should be fixed high or low during
operations since WP does not provide a latch function.
Write Protect Area
Write protect area
WP pin status 8k bit
16k bit
32k bit
64k bit
V
IH
V
IL
Upper 1/2 (4k bit)
Upper 1/2 (8k bit)
Upper 1/4 (8k bit)
Upper 1/4 (16k bit)
Normal read/write operation
相關(guān)PDF資料
PDF描述
HN58X2532NI HN58X2532I/HN58X2564I Datasheet
HN58X2532TI HN58X2532I/HN58X2564I Datasheet
HN58X2564FPI HN58X2532I/HN58X2564I Datasheet
HN58X2564NI HN58X2532I/HN58X2564I Datasheet
HN58X2564TI HN58X2532I/HN58X2564I Datasheet
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